A compact and reconfigurable low noise amplifier employing combinational active inductors and composite resistors feedback techniques

A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.

Fuzzy System Design Using Current Amplifier for 20 nm CMOS Technology

In the recent decade,different researchers have performed hardware implementation for different applications covering various areas of experts.In this research paper,a novel analog design and implementation of different steps of fuzzy systems with current differencing buffered amplifier(CDBA)are proposed with a compact structure that can be used in many signal processing applications.The proposed circuits are capable of wide input current range,simple structure,and are highly linear.Different electrical parameters were compared for the proposed fuzzy system when using different membership functions.The novelty of this paper lies in the electronic implementation of different steps for realizing a fuzzy system using current amplifiers.When the power supply voltage of CDBA is 2V,it results in 155mW,power dissipation;4.615KΩ,input resistance;366KΩ,output resistances;and 189.09 dB,common-mode rejection ratio.A 155.519 dB,voltage gain,and 0.76V/μs,the slew rate is analyzed when the power supply voltage of CDBAis 3V.The fuzzy system is realized in 20nm CMOS technology and investigated with an output signal of high precision and high speed,illustrating that it is suitable for realtime applications.In this research paper,a consequence of feedback resistance on the adder circuit and the defuzzified circuit is also analyzed and the best results are obtained using 100K resistance.The structure has a low hardware complexity leading to a low delay and a rather high quality.

A low noise CMOS RF front-end for UWB 6-9 GHz applications

An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented.A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB,an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of-12.6 dBm while in the low gain mode.This RF front-end consumes 17 mA from a 1.2 V supply voltage.