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Design and Implementation of Efficient Reversible Arithmetic and Logic Unit
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作者 Subramanian Saravanan Ila Vennila Sudha Mohanram 《Circuits and Systems》 2016年第6期630-642,共13页
In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improv... In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations. 展开更多
关键词 reversible Logic Gates reversible Logic circuits reversible Multiplier circuits Vedic Multiplier ALU
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Design and Implementation of an Efficient Reversible Comparator Using TR Gate
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作者 Subramanian Saravanan Ila Vennila Sudha Mohanram 《Circuits and Systems》 2016年第9期2578-2592,共15页
Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computin... Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output. 展开更多
关键词 reversible Logic Gates reversible Logic circuits (Very Large Scale Integration) VLSI Design
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