A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given....A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.展开更多
The pathogen,pathogenic mechanism and incidence condition of pear ring rot,and its damage on fruits,branches and leaves are summarized in the paper. The control measures including plant quarantine,agricultural control...The pathogen,pathogenic mechanism and incidence condition of pear ring rot,and its damage on fruits,branches and leaves are summarized in the paper. The control measures including plant quarantine,agricultural control,physical control,biological control,and chemical control against pear ring rot are reviewed.展开更多
A double silicon on insulator（DSOI） structure was introduced based on fully depleted SOI（FDSOI）technology.The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to ...A double silicon on insulator（DSOI） structure was introduced based on fully depleted SOI（FDSOI）technology.The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices.Based on DSOI ring oscillator（OSC）,this paper focused on the theoretical analysis and electrical test of how the OSC＇s frequency being influenced by the back gate electrodes（soi2n,soi2p）.The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias.According to the different requirements of the circuit designers,the circuit performance could be improved by positive soi2 n and negative soi2 p,and the power consumption could be reduced by negative soi2n and positive soi2p.The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing.展开更多
文摘A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.
文摘The pathogen,pathogenic mechanism and incidence condition of pear ring rot,and its damage on fruits,branches and leaves are summarized in the paper. The control measures including plant quarantine,agricultural control,physical control,biological control,and chemical control against pear ring rot are reviewed.
文摘A double silicon on insulator（DSOI） structure was introduced based on fully depleted SOI（FDSOI）technology.The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices.Based on DSOI ring oscillator（OSC）,this paper focused on the theoretical analysis and electrical test of how the OSC＇s frequency being influenced by the back gate electrodes（soi2n,soi2p）.The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias.According to the different requirements of the circuit designers,the circuit performance could be improved by positive soi2 n and negative soi2 p,and the power consumption could be reduced by negative soi2n and positive soi2p.The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing.
