To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorit...To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.展开更多
The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass ...The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.展开更多
A robust digital watermarking algorithm is proposed based on quaternion wavelet transform(QWT) and discrete cosine transform(DCT) for copyright protection of color images. The luminance component Y of a host color ima...A robust digital watermarking algorithm is proposed based on quaternion wavelet transform(QWT) and discrete cosine transform(DCT) for copyright protection of color images. The luminance component Y of a host color image in YIQ space is decomposed by QWT, and then the coefficients of four low-frequency subbands are transformed by DCT. An original binary watermark scrambled by Arnold map and iterated sine chaotic system is embedded into the mid-frequency DCT coefficients of the subbands. In order to improve the performance of the proposed algorithm against rotation attacks, a rotation detection scheme is implemented before watermark extracting. The experimental results demonstrate that the proposed watermarking scheme shows strong robustness not only against common image processing attacks but also against arbitrary rotation attacks.展开更多
An adaptive beamforming algorithm named robust joint iterative optimizationdirection adaptive （RJIO-DA） is proposed for large-array scenarios. Based on the framework of minimum variance distortionless response （MVD...An adaptive beamforming algorithm named robust joint iterative optimizationdirection adaptive （RJIO-DA） is proposed for large-array scenarios. Based on the framework of minimum variance distortionless response （MVDR）, the proposed algorithm jointly updates a transforming matrix and a reduced-rank filter. Each column of the transforming matrix is treated as an independent direction vector and updates the weight values of each dimension within a subspace. In addition, the direction vector rotation improves the performance of the algorithm by reducing the uncertainties due to the direction error. Simulation results show that the RJIO-DA algorithm has lower complexity and faster convergence than other conventional reduced-rank algorithms.展开更多
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z280)
文摘To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.
文摘The implementation of the coordinate rotational digital computer （CORDIC） algorithm with wave pipelining technique on field programmable gate array （FPGA） is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330 MHz, whichis a little lower than the speed of 336 MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3 ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.
基金supported by the National Natural Science Foundation of China(Nos.61601467,61379102,61502498,U1433105 and U1433120)the Fundamental Research Funds for the Central Universities(3122017044)
文摘A robust digital watermarking algorithm is proposed based on quaternion wavelet transform(QWT) and discrete cosine transform(DCT) for copyright protection of color images. The luminance component Y of a host color image in YIQ space is decomposed by QWT, and then the coefficients of four low-frequency subbands are transformed by DCT. An original binary watermark scrambled by Arnold map and iterated sine chaotic system is embedded into the mid-frequency DCT coefficients of the subbands. In order to improve the performance of the proposed algorithm against rotation attacks, a rotation detection scheme is implemented before watermark extracting. The experimental results demonstrate that the proposed watermarking scheme shows strong robustness not only against common image processing attacks but also against arbitrary rotation attacks.
基金supported by the National Science&Technology Pillar Program(2013BAF07B03)Zhejiang Provincial Natural Science Foundation of China(LY13F010009)
文摘An adaptive beamforming algorithm named robust joint iterative optimizationdirection adaptive （RJIO-DA） is proposed for large-array scenarios. Based on the framework of minimum variance distortionless response （MVDR）, the proposed algorithm jointly updates a transforming matrix and a reduced-rank filter. Each column of the transforming matrix is treated as an independent direction vector and updates the weight values of each dimension within a subspace. In addition, the direction vector rotation improves the performance of the algorithm by reducing the uncertainties due to the direction error. Simulation results show that the RJIO-DA algorithm has lower complexity and faster convergence than other conventional reduced-rank algorithms.
