A layered network model for optical transport networks is proposed in this paper,which involves Internet Protocol(IP) ,Synchronous Digital Hierarchy(SDH) and Wavelength Division Mul-tiplexing(WDM) layers. The strategy...A layered network model for optical transport networks is proposed in this paper,which involves Internet Protocol(IP) ,Synchronous Digital Hierarchy(SDH) and Wavelength Division Mul-tiplexing(WDM) layers. The strategy of Dynamic Joint Routing and Resource Allocation(DJRRA) and its algorithm description are also presented for the proposed layered network model. DJRRA op-timizes the bandwidth usage of interface links between different layers and the logic links inside all layers. The simulation results show that DJRRA can reduce the blocking probability and increase network throughput effectively,which is in contrast to the classical separate sequential routing and resource allocation solutions.展开更多
A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional ...A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6. 104mm× 6. 620mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.展开更多
This paper presents a universal field programmable gate array（FPGA） programmable routing circuit,focusing primarily on a delay optimization.Under the precondition of the routing resource＇s flexibility and routabili...This paper presents a universal field programmable gate array（FPGA） programmable routing circuit,focusing primarily on a delay optimization.Under the precondition of the routing resource＇s flexibility and routability,the number of programmable interconnect points（PIP） is reduced,and a multiplexer（MUX） plus a BUFFER structure is adopted as the programmable switch.Also,the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit,respectively.All of the above features ensure that the whole FPGA chip is highly repeatable,and the signal delay is uniform and predictable over the total chip.Meanwhile,the BUFFER driver is optimized to decrease the signal delay by up to 5%.The proposed routing circuit is applied to the Fudan programmable device（FDP） FPGA,which has been taped out with an SMIC 0.18-μm logic 1P6M process.The test result shows that the programmable routing resource works correctly,and the signal delay over the chip is highly uniform and predictable.展开更多
基金the Science & Technology Foundation of Huawei Ltd. (No.YJCB2005040SW)the Creative Foundation of Xidian University (No.05030).
文摘A layered network model for optical transport networks is proposed in this paper,which involves Internet Protocol(IP) ,Synchronous Digital Hierarchy(SDH) and Wavelength Division Mul-tiplexing(WDM) layers. The strategy of Dynamic Joint Routing and Resource Allocation(DJRRA) and its algorithm description are also presented for the proposed layered network model. DJRRA op-timizes the bandwidth usage of interface links between different layers and the logic links inside all layers. The simulation results show that DJRRA can reduce the blocking probability and increase network throughput effectively,which is in contrast to the classical separate sequential routing and resource allocation solutions.
文摘A novel Fudan programmable logic chip （FDP） was designed and implemented with a SMIC 0. 18μm CMOS logic process. The new 3-LUT based logic cell circuit increases logic density about 11% compared with a traditional 4-input LUT. The unique hierarchy routing fabrics and effective switch box optimize the routing wire segments and make it possible for different lengths to connect directly. The FDP contains 1,600 programmable logic cells, 160 programmable I/O, and 16kbit dual port block RAM. Its die size is 6. 104mm× 6. 620mm, with the package of QFP208. The hardware and software cooperation tests indicate that FDP chip works correctly and efficiently.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z285)the National Natural Science Foundation of China (No. 60876015)
文摘This paper presents a universal field programmable gate array（FPGA） programmable routing circuit,focusing primarily on a delay optimization.Under the precondition of the routing resource＇s flexibility and routability,the number of programmable interconnect points（PIP） is reduced,and a multiplexer（MUX） plus a BUFFER structure is adopted as the programmable switch.Also,the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit,respectively.All of the above features ensure that the whole FPGA chip is highly repeatable,and the signal delay is uniform and predictable over the total chip.Meanwhile,the BUFFER driver is optimized to decrease the signal delay by up to 5%.The proposed routing circuit is applied to the Fudan programmable device（FDP） FPGA,which has been taped out with an SMIC 0.18-μm logic 1P6M process.The test result shows that the programmable routing resource works correctly,and the signal delay over the chip is highly uniform and predictable.
