This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,t...This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method展开更多
The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic ...The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.展开更多
Run-length limited(RLL)codes can facilitate reliable data transmission and provide flicker-free illumination in visible light communication(VLC)systems.We propose novel high-rate RLL codes,which can improve error perf...Run-length limited(RLL)codes can facilitate reliable data transmission and provide flicker-free illumination in visible light communication(VLC)systems.We propose novel high-rate RLL codes,which can improve error performance and mitigate flicker.Two RLL coding schemes are developed by designing the finite-state machine to further enhance the coding gain by improving the minimum Hamming distance and using the state-splitting method to realize small state numbers.In our RLL code design,the construction of the codeword set is critical.This codeword set is designed considering the set-partitioning algorithm criterion.The flicker control and minimum Hamming distance of the various proposed RLL codes are described in detail,and the flicker performances of different codes are compared based on histograms.Simulations are conducted to evaluate the proposed RLL codes in on-off keying modulation VLC systems.Simulation results demonstrate that the proposed RLL codes achieve superior error performance to the existing RLL codes.展开更多
文摘This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method
基金supported by the Shenzhen Government R&D Project under Grant No.JC200903160361A
文摘The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.
基金Project supported by the Fundamental Research Funds for the Central Universities,China(No.2020QN15)。
文摘Run-length limited(RLL)codes can facilitate reliable data transmission and provide flicker-free illumination in visible light communication(VLC)systems.We propose novel high-rate RLL codes,which can improve error performance and mitigate flicker.Two RLL coding schemes are developed by designing the finite-state machine to further enhance the coding gain by improving the minimum Hamming distance and using the state-splitting method to realize small state numbers.In our RLL code design,the construction of the codeword set is critical.This codeword set is designed considering the set-partitioning algorithm criterion.The flicker control and minimum Hamming distance of the various proposed RLL codes are described in detail,and the flicker performances of different codes are compared based on histograms.Simulations are conducted to evaluate the proposed RLL codes in on-off keying modulation VLC systems.Simulation results demonstrate that the proposed RLL codes achieve superior error performance to the existing RLL codes.
