This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal te...This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscilla- tion-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscilla- tion-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.展开更多
This paper proposes a dynamic adaptive coscheduling model DASIC to take advantage of excess available resources in a network of workstations (NOW).Besides coscheduling related subtasks dynamically, DASIC can scale up ...This paper proposes a dynamic adaptive coscheduling model DASIC to take advantage of excess available resources in a network of workstations (NOW).Besides coscheduling related subtasks dynamically, DASIC can scale up or down the process space depending upon the number of available processors on an NOW.Based on the dynamic idle processor group (IPG), DASIC employs three modules:the coscheduling module, the scalable scheduling module and the load balancing module, and uses six algorithms to achieve scalability. A simplified DASIC was also implemented, and experimental results are presented in this paper, which show that it can maximize system utilization, and achieve task parallelism as much as possible.展开更多
文摘This paper presents a standard scalable and reconfigurable design for testability (SR DfT) in order to increase ac- cessibility to deeply embedded A/MS cores and to limit application of costly off-chip mixed-signal testers. SR DfT is an oscilla- tion-based wrapper compatible with digital embedded core-based SoC test methodologies. The impact of the optimized oscilla- tion-based wrapper design on MS SoC testing is evaluated in two directions: area and test time. Experimental results are presented for several SoCs from the ITC’02 test benchmarks with inclusion of eight analog filters.
文摘This paper proposes a dynamic adaptive coscheduling model DASIC to take advantage of excess available resources in a network of workstations (NOW).Besides coscheduling related subtasks dynamically, DASIC can scale up or down the process space depending upon the number of available processors on an NOW.Based on the dynamic idle processor group (IPG), DASIC employs three modules:the coscheduling module, the scalable scheduling module and the load balancing module, and uses six algorithms to achieve scalability. A simplified DASIC was also implemented, and experimental results are presented in this paper, which show that it can maximize system utilization, and achieve task parallelism as much as possible.
