Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for sil...Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.展开更多
Balanced wrapper scan chains are desirable for system-on-chip (SoC) testing because they minimize the time required to transport the test data. A new heuristic algorithm is proposed based on mean- value approximation ...Balanced wrapper scan chains are desirable for system-on-chip (SoC) testing because they minimize the time required to transport the test data. A new heuristic algorithm is proposed based on mean- value approximation and implement fast re-optimization as a subsequence of an earlier best-fit-decrease (BFD) method. The mean length of each scan chain was introduced as an approximation target to balance different scan chains and hence saved testing time. Experimental results present both for assumed arbitrary cores and cores from ITC’02 benchmark and show the effectiveness of the algorithm. The proposed algorithm can provide more balanced wrapper design efficiently for the test scheduling stage.展开更多
基金the National Natural Science Foundation of China(No. 60633060)the National Basic Research and Development(973) Program of China (No. 2005CB321604)
文摘Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.
基金the National Key Basic Research and Development (973) Program of China(No. 2005CB321604)the National Natural Science Foundation of China (No. 60633060).
文摘Balanced wrapper scan chains are desirable for system-on-chip (SoC) testing because they minimize the time required to transport the test data. A new heuristic algorithm is proposed based on mean- value approximation and implement fast re-optimization as a subsequence of an earlier best-fit-decrease (BFD) method. The mean length of each scan chain was introduced as an approximation target to balance different scan chains and hence saved testing time. Experimental results present both for assumed arbitrary cores and cores from ITC’02 benchmark and show the effectiveness of the algorithm. The proposed algorithm can provide more balanced wrapper design efficiently for the test scheduling stage.
