An on-chip power-on reset circuit with a brown-out detection capability is implemented in a 0. 18 μm CMOS. A pF-order capacitor is charged with a proportional-to-absolute-temperature （PTAT） current from a bandgap r...An on-chip power-on reset circuit with a brown-out detection capability is implemented in a 0. 18 μm CMOS. A pF-order capacitor is charged with a proportional-to-absolute-temperature （PTAT） current from a bandgap reference with limited loop bandwidth and slow start-up feature, to generate a reset signal with high robustness and wide-range supply rise time. An embedded brown- out detector based on complementary voltage-to-current （V-to-I） conversion and current comparison can accurately respond to the brown-out event with high robustness over process and temperature when the supply is lower than 1.5 V and the brown-out duration is longer than 0. 1 ms. The presented design with embedded offset voltage cancellation consumes a quiescent current of 8. 5 μA from a 1. 8 V supply and works over ambient temperature of -40° to 120°.展开更多
基金Supported by the National Natural Science Foundation of China(6130603761201182)
文摘An on-chip power-on reset circuit with a brown-out detection capability is implemented in a 0. 18 μm CMOS. A pF-order capacitor is charged with a proportional-to-absolute-temperature （PTAT） current from a bandgap reference with limited loop bandwidth and slow start-up feature, to generate a reset signal with high robustness and wide-range supply rise time. An embedded brown- out detector based on complementary voltage-to-current （V-to-I） conversion and current comparison can accurately respond to the brown-out event with high robustness over process and temperature when the supply is lower than 1.5 V and the brown-out duration is longer than 0. 1 ms. The presented design with embedded offset voltage cancellation consumes a quiescent current of 8. 5 μA from a 1. 8 V supply and works over ambient temperature of -40° to 120°.
