Design and Implementation of a Bootstrap Trust Chain

The chain of trust in bootstrap process is the basis of whole system trust in the trusted computing group （TCG） definition. This paper presents a design and implementation of a bootstrap trust chain in PC based on the Windows and today＇s commodity hardware, merely depends on availability of an embedded security module （ESM）. ESM and security enhanced BIOS is the root of trust, PMBR （Pre-MBR） checks the integrity of boot data and Windows kernel, which is a checking agent stored in ESM. In the end, the paper analyzed the mathematic expression of the chain of trust and the runtime performance compared with the common booring process. The trust chain bootstrap greatly strengthens the security of personal computer system, and affects the runtime performance with only adding about 12% booting time.

A Steganography-Based Optical Image Encryption System Using RGB Channel Integration

An optical image encryption system with adaptive steganography using red, green, and blue （RGB） channel integration is proposed. The optical image encryption system employs a double random phase encoding algorithm to encrypt and decrypt color images. The RGB channel in a color image is first integrated into a large grayscale image. Then the integrated image is encrypted by two random phase masks. The secret data is then embedded into the encrypted image with a specific hiding sequence generated by the zero-LSB （least significant bits） sorting technique which is a content-dependent and low distortion data embedding method. Experimental results show that the proposed, method has a good performance in both hiding capacity and decrypted image quality.

Transmission network expansion planning with embedded constraints of short circuit currents and N-1 security

An approach of transmission network expan-sion planning with embedded constraints of short circuit currents and N-1 security is proposed in this paper.The problem brought on by the strong nonlinearity property of short circuit currents is solved with a linearization method based on the DC power flow.The model can be converted to a mixed-integer linear programming problem,realizing the optimization of planning model that considers the constraints of linearized short circuit currents and N-1 security.To compensate the error caused by the assump-tions of DC power flow,the compensation factor is pro-posed.With this factor,an iterative algorithm that can compensate the linearization error is then presented.The case study based on the IEEE 118-bus system shows that the proposed model and approach can be utilized to:opti-mize the construction strategy of transmission lines;ensure the N-1 security of the network;and effectively limit the short circuit currents of the system.

BORON:an ultra-lightweight and low power encryption design for pervasive computing

We propose an ultra-lightweight, compact, and low power block cipher BORON. BORON is a substitution and permutation based network, which operates on a 64-bit plain text and supports a key length of 128/80 bits. BORON has a compact structure which requires 1939 gate equivalents(GEs) for a 128-bit key and 1626 GEs for an 80-bit key. The BORON cipher includes shift operators, round permutation layers, and XOR operations. Its unique design helps generate a large number of active S-boxes in fewer rounds, which thwarts the linear and differential attacks on the cipher. BORON shows good performance on both hardware and software platforms. BORON consumes less power as compared to the lightweight cipher LED and it has a higher throughput as compared to other existing SP network ciphers. We also present the security analysis of BORON and its performance as an ultra-lightweight compact cipher. BORON is a well-suited cipher design for applications where both a small footprint area and low power dissipation play a crucial role.

Implementation of PRINCE with resource-efficient structures based on FPGAs

In this era of pervasive computing, low-resource devices have been deployed in various fields. PRINCE is a lightweight block cipher designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for PRINCE components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components,we propose three new hardware architectures for PRINCE. The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, low-cost, and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The low-cost architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of PRINCE, the new low-cost architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight,latency-critical applications.

Embedded fuzzing:a review of challenges,tools,and solutions

Fuzzing has become one of the best-established methods to uncover software bugs.Meanwhile,the market of embedded systems,which binds the software execution tightly to the very hardware architecture,has grown at a steady pace,and that pace is anticipated to become yet more sustained in the near future.Embedded systems also beneft from fuzzing,but the innumerable existing architectures and hardware peripherals complicate the development of general and usable approaches,hence a plethora of tools have recently appeared.Here comes a stringent need for a systematic review in the area of fuzzing approaches for embedded systems,which we term'embedded fuzzing"for brevity.The inclusion criteria chosen in this article are semi-objective in their coverage of the most relevant publication venues as well as of our personal judgement.The review rests on a formal definition we develop to represent the realm of embedded fuzzing.It continues by discussing the approaches that satisfy the inclusion criteria,then defines the relevant elements of comparison and groups the approaches according to how the execution environment is served to the system under test.The resulting review produces a table with 42 entries,which in turn supports discussion suggesting vast room for future research due to the limitations noted.