Most existing system-on-chip （SoC） architectures are for microprocessor-centric designs. They are not suitable for computing intensive SoCs, which have their own conflgurability, extendibility, perform- ance, and da...Most existing system-on-chip （SoC） architectures are for microprocessor-centric designs. They are not suitable for computing intensive SoCs, which have their own conflgurability, extendibility, perform- ance, and data exchange characteristics. This paper analyzes these characteristics and gives design princi- ples for computing intensive SoCs. Three architectures suitable for different situations are compared with selection criteria given. The architectural design of a high performance network security accelerator （HPNSA） is used to elaborate on the design techniques to fully exploit the performance potential of the ar- chitectures. A behavior-level simulation system is implemented with the C＋＋ programming language to evaluate the HPNSA performance and to obtain the optimum system design parameters. Simulations show that this architecture provides high performance data transfer.展开更多
基金Supported by the National Natural Science Foundation of China (No. 60576027)the National High-Tech Research and Development (863) Program of China (No. 2006AA01Z415)
文摘Most existing system-on-chip （SoC） architectures are for microprocessor-centric designs. They are not suitable for computing intensive SoCs, which have their own conflgurability, extendibility, perform- ance, and data exchange characteristics. This paper analyzes these characteristics and gives design princi- ples for computing intensive SoCs. Three architectures suitable for different situations are compared with selection criteria given. The architectural design of a high performance network security accelerator （HPNSA） is used to elaborate on the design techniques to fully exploit the performance potential of the ar- chitectures. A behavior-level simulation system is implemented with the C＋＋ programming language to evaluate the HPNSA performance and to obtain the optimum system design parameters. Simulations show that this architecture provides high performance data transfer.
