Voltage-Mode Universal Biquad Filter Employing Single Voltage Differencing Differential Input Buffered Amplifier

A new multi function voltage-mode universal biquadratic filter using single Voltage Differencing Differential Input Buffered Amplifier (VD-DIBA), two capacitors and one resistor is proposed. The proposed configuration has four inputs and one output and can realize all the five standard filters from the same circuit configuration. The presented biquad filter offers low active and passive sensitivities. The validity of proposed universal biquadratic filter has been verified by SPICE simulation using 0.35 μm MIETEC technology.

Low Phase Noise and Wide Tuning Range VCO Using the MOS Differential Amplifier with Active Load

We demonstrate the design of a novel voltage-controlled oscillator (VCO), which is based on a metal-oxide-semiconductor field-effect transistor (MOS) differential amplifier with active load. This VCO achieves low phase noise and wide tuning range. The phase noise is –120 dBc/Hz at 600 KHz offset from a 1.216 GHz carrier frequency. This value is comparable to that of a LC-based integrated oscillator. The operating frequency can be tuned from 117 MHz to 1.216 GHz with the supply voltage varying from 1.3 V to 3.3 V. Therefore, the tuning range is about 90.38% which is larger than most of the LC and ring oscillator. The VCO circuit, which is constructed using a standard 0.35 μm CMOS technology, occupies only 26.25 × 7.52 μm2 die area and dissipated 10.56 mW under a 3.3 V supply voltage.

Semiconductor optical amplifier used as regenerator for degraded differential phase-shift keying signals

Phase and amplitude regeneration are necessary for degraded differential phase-shift keying communication sys- tems. This paper proposes a regenerator based on semiconductor optical amplifier for differential phase-shift keying signals. The key regeneration mechanism is theoretically analysed. The effectiveness of semiconductor optical amplifier based regenerator is demonstrated by comparing the bit error rate and eye diagrams before and after regeneration for 40-Cbit/s differential phase-shift keying 1080-km transmission systems. The results show that regeneration effects are very well. Bit error rate is tess than 10-12 with the regenerator.

A 9 - 10.6 GHz Microstrip Antenna—UWB Low Noise Amplifier with Differential Noise Canceling Technique for IoT Applications

An ultra-wide band (UWB) receiver front-end that operates at the UWB frequency range, starting from 9 GHz - 10.6 GHz is proposed in this paper. The proposed system consists of an off-chip microstrip antenna and CMOS differential low noise amplifier with a differential noise canceling (DNC) technique. The proposed antenna is trapezoidal dipole shaped with balun and printed on a low-cost FR4 substrate with dimensions 10 × 10 × 0.8 mm3. The balun circuit integrated with the ground antenna to improve the antenna impedance matching. Noise canceling is obtained by using a differential block with each stage having 2 amplifiers that generate differential signals, subtracted to improve total noise performance. The proposed DNC block improves NF by 50% while increasing total power consumption with only 0.1 Mw. The differential CMOS cascode LNA with DNC block is implemented using UMC 0.13 μm CMOS process, exhibits a flat gain of 19 dB, maximum noise figure of 2.75 dB, 1 dB compression point −16 dBm and 3rd order intercept point (IIP3) −10 dBm. The proposed system has total DC power consumption of 2.8 mW at 1.2 V power supply.

<i>A Brief Review</i>: Stage-Convertible Power Amplifier Using Differential Line Inductor

In this review article, a stage-convertible RF power amplifier designed with a 0.18-μm RF CMOS process is described. A method to implement a low-power matching network is an essential technology for the stage-convertible power amplifier. Various low-power matching networks with distributed active transformers as an output power combiner are compared in terms of the amounts of undesired coupling, the chip size, and the amount of power loss. The feasibility of a differential line inductor for the stage-convertible power amplifier is assessed and explained. Finally, we show that the differential line inductor is a realistic means of reducing the overall chip size, enhancing the quality factor of the matching network, and minimizing the undesired coupling between the inter-stage matching network and any output matching network. Additionally, the operating mechanism of the stage-convertible power amplifier using the differential line inductor for a low-power matching network is described in detail.

Current Mode Universal Filter Using Single Current Controlled Differential Difference Current Conveyor Transconductance Amplifier

This research paper contains a new electronically tunable current-mode biquadratic universal filter using a new active building block;current controlled differential difference current conveyor transconductance amplifier (CCDDCCTA). The proposed filter provides the following important and desirable features: (i) One can use only one CCDDCCTA and two capacitors;(ii) One can get low pass (LP), band pass (BP), high pass (HP), notch (NF) and all pass (AP) current responses from the same configuration without any alteration;(iii) Passive components are grounded, which ease the integrated circuit implementation;(iv) Responses are electronically tunable;and (v) Sensitivity is low. Moreover, the non-ideality analysis shows that the parasitic passive components can be compensated for the proposed circuit. The functionality of the design is verified through SPICE simulations using 0.25 μm CMOS TSMC technology process parameters. Simulation result agrees well with the theoretical analysis.

A Grounded Capacitor Differentiator Using Current Feedback Amplifier

A new non-inverting RC active differentiator network base on a current feedback amplifier and using a grounded capacitor is described. Small time constant can be achieved by adjusting a single grounded resistor. Because the output impedance of the CFA is very low, the output terminal of the proposed circuit can be directly connected to the next stage. Experimental results that confirm theoretical analysis are presented.

Inductorless CMOS Low Noise Amplifier for Multiband Application in 0.1–1.2 GHz

A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

For the conventional single-ended eFuse cell,sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms.A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell.Also,a sensing circuit of sense amplifier is proposed,based on D flip-flop structure to implement a simple sensing circuit.Furthermore,a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse.When an 8 bit eFuse OTP IP is designed with 0.18 μm standard CMOS logic of TSMC,the layout dimensions are 229.04 μm× 100.15 μm.All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

On Design of Memristive Amplifier Circuits

Amplifiers are essential building blocks of a majority of the mixed signal circuits that are used in the development of cognitive computing architectures. Their implementation and use is challenged by the second order effects that dominate the MOSFET operations with reduction in the technology size and scale. The ability to program the amplifiers once fabricated becomes an even more challenging problem as it warrants the use of multiple circuit components that lowers circuit performance and in turn outweighs the advantages of generalisation abilities. In this paper, a reconfigurable set of amplifier circuits are proposed based on quantised conductance devices in combination with MOSFET devices. The presented circuits form the basic configurations for the memristor based amplifiers, and show promising performance results in terms of power dissipation, on-chip area and THD values.

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

一种高共模电压集成差分放大器的设计

针对差分放大器芯片国产化的需求,基于兼容金属薄膜电阻40 V双极工艺,设计一款高共模抑制比(Common Mode Rejection Ratio,CMRR)、±120 V共模输入电压的集成差分放大器。文章介绍了高共模电压差分放大器的基本原理和结构组成,分析了差分放大器的设计难点,分别为共模抑制比、输入失调电流以及增益误差,采用片内集成金属薄膜电阻结合激光在线修调技术实现高共模抑制比、通过改进型的基极电流补偿结构降低了输入失调电流,减少输入失调电流对电路采样精度的影响,采用改进型达林顿管提高放大器的开环增益,降低放大器的增益误差。整体芯片尺寸为2.82 mm×2.02 mm,采用±15 V双电源供电,静态电流为1.36 mA。流片后的测试结果表明:差分放大器在正常供电时,共模抑制比达到85 dB,输入失调电流仅为84 pA,失调电流的补偿精度达到98.1%,增益误差为0.02%。

A single-to-differential low-noise amplifier with low differential output imbalance

This paper presents a single-ended input differential output low-noise amplifier intended for GPS applications. We propose a method to reduce the gain/amplitude and phase imbalance of a differential output exploiting the inductive coupling of a transformer or center-tapped differential inductor.A detailed analysis of the theory of imbalance reduction,as well as a discussion on the principle of choosing the dimensions of a transformer,are given.An LNA has been implemented using TSMC 0.18μm technology with ESD-protected.Measurement on board shows a voltage gain of 24.6 dB at 1.575 GHz and a noise figure of 3.2 dB.The gain imbalance is below 0.2 dB and phase imbalance is less than 2 degrees.The LNA consumes 5.2 mA from a 1.8 V supply.

Genetic Differentiation Caused by Chromium Treatment in <i>Leersia hexandra</i>Swartz Revealed by RAPD Analysis

Randomly amplified polymorphic DNA (RAPD) technique was applied to assess the genetic variations and phylogenetic relationships in genetic differentiation within 4 Chromium-treatment Leersia hexandra. The fresh leaves of Leersia hexandra cultivated on the condition of chrome pollution and exogenous organic acids were used as experimental material. The genomic DNA of Leersia hexandra was extracted by using CTAB method. The results showed that different samples of Leersia hexandra exhibited DNA polymorphism when using the random primer S43, S51and S55 as the primers in the RAPD reaction. One specific DNA band about 1000 bp was found in the sample which treated with 10 mmol/L concentration EDTA when used the S43 primer to RAPD. The obvious differences between different EDTA-treatment levels suggest that EDTA has certain effects on enrichment to heavy metals of Leersia hexandra, it will be more favored to Leersia hexandra accumulation of chromium when EDTA concentration increased.

面向强周期振动干扰的涡街流量计系统研制

涡街流量计是流体振动型流量仪表,易受管道振动、流场扰动等影响,在小流量条件下测量误差较大,尤其在强振动干扰下涡街信号被淹没,无法准确测量。本文研制抗强周期振动干扰的涡街流量计系统,采用带有电压负反馈的差动式电荷放大器,提高小流量信号的放大能力;提出基于频移策略的频率方差算法,减少强周期振动干扰的影响。首先通过频移策略降低相近频率的影响,然后根据流量信号与周期振动干扰的频带宽度不同,通过计算和比较频率方差,判定流量信号频率。研制了涡街流量计信号处理系统并实验,结果表明,研制的系统扩展了量程下限,且在强周期振动干扰条件下可以准确提取信号,精度提升1个数量级。

基于0.18μm CMOS工艺的300GHz高响应度探测器

基于0.18μm CMOS工艺设计了一种300 GHz高响应度探测器。该探测器集成了双馈差分天线和双场效应管(FET)对称差分自混频电路。双馈差分天线较单馈天线有更高的精确度及更优的抗干扰性。差分自混频电路能有效地抑制共模信号,减小噪声输入。双场效应管后增加一级放大电路,将自混频电路输出的微弱信号进一步放大以增大响应度。天线与电路间的匹配网络实现了信号的最大功率传输。在全波电磁场仿真软件HFSS下对双馈天线进行建模与仿真优化,并与电路进行联合仿真。结果显示探测器在栅源电压为0.43 V、输入功率为-40 dBm时,最大响应度为11.25 kV/W,最小噪声等效功率为115pW/√Hz。

基于集成运放的低频信号共模和差模成分的分离

传导干扰包含共模干扰和差模干扰,需要采取不同措施来抑制共模干扰和差模干扰.如果一对对地模拟信号中既含有共模成分又含有差模成分,工程上需要将其分离,基于集成运算放大器构建了一个同相加法运算电路和一个减法运算电路,利用这个加法和减法运算电路可对50kHz以下低频输入信号中的共模成分和差模成分进行分离.用电路仿真的方法验证了电路对信号中共模和差模成分分离的有效性,所构建的电路提供了一种分离50kHz以下低频信号中共模成分和差模成分的新方法.

基于SSA ELM和自适应差分进化算法的拉曼放大器设计

提出了一种将樽海鞘群算法优化极限学习机与自适应差分进化算法相结合的方法,并利用该方法优化多泵浦拉曼光纤放大器的参数配置。采用极限学习机构建泵浦参数和拉曼增益之间的非线性映射,并利用樽海鞘群优化算法对极限学习机参数进行优化获得最佳模型。对比分析了上述模型与BP神经网络和传统的极限学习机模型在评价指标方面的差异,结果表明本文所提出的模型预测性能较好。为了提高增益平坦性,利用自适应差分进化算法优化泵浦参数,得到最佳的参数配置。仿真结果表明,利用该方法设计出的拉曼放大器达到了预期效果,其目标增益与预测增益的最大误差不超过05dB。该方法为今后拉曼光纤放大器的设计提供了一种新的思路方法。

一种高增益、高带宽全差分运算放大器的设计

采用增益提升(Gain-boosting)技术,使用2个三输入管的折叠式共源共栅运算放大器(运放)作为辅助运放,设计了一种宽输入共模范围的高增益、高带宽的全差分运算放大器。主运放输入部分由一对NMOS管和一对PMOS管共同构成,其输入跨导提高至由单MOS管构成的运放输入跨导的2倍。主运放输入跨导的提高间接提升了主运放的增益和带宽。而辅助运放在不改变主运放带宽的同时,通过降低主运放的主极点增大输出阻抗,再次提升主运放的增益,达到了高增益、高带宽的目的。该运算放大器采用商用55 nm CMOS工艺设计,经仿真可得,当负载电容为5 pF时,运放低频增益为115 dB,增益带宽积为209 MHz,总功耗为2.8 mW。