Optimizing Factory Performance for Unit Cost in Semiconductor Manufacturing

The integrated circuit (IC) manufacturing process is capital intensive and complex. The production process of unit product (or die, as it is commonly referred to) takes several weeks. Semiconductor factories (fabs) continuously attempt to improve their productivity, as measured in output and cycle time (or mean flow time). The conflicting objective of producing maximum units at minimal production cycle time and at the highest quality, as measured by die yield, is discussed in this paper. The inter-related effects are characterized, and a model is proposed to address this multi-objective function. We then show that, with this model, die cost can be optimized for any given operating conditions of a fab. A numerical example is provided to illustrate the practicality of the model and the proposed optimization method.

Evaluation System and Correlation Analysis for Determining the Performance of a Semiconductor Manufacturing System

Numerous performance indicators exist for semiconductor manufacturing systems.Several studies have been conducted regarding the performance optimization of semiconductor manufacturing systems.However,because of the complex manufacturing processes,potential complementary or inhibitory correlations may exist among performance indicators,which are difficult to demonstrate specifically.To analyze the correlation between the performance indicators,this study proposes a performance evaluation system based on the mathematical significance of each performance indicator to design statistical schemes.Several samples can be obtained by conducting simulation experiments through the performance evaluation system.The Pearson correlation coefficient method and canonical correlation analysis are used on the received samples to analyze linear correlations between the performance indicators.Through the investigation,we found that linear and other complex correlations exist between the performance indicators.This finding can contribute to our future studies regarding performance optimization for the scheduling problems of semiconductor manufacturing.

Scheduling a Single-Arm Multi-Cluster Tool With a Condition-Based Cleaning Operation

As wafer circuit widths shrink less than 10 nm,stringent quality control is imposed on the wafer fabrication processes. Therefore, wafer residency time constraints and chamber cleaning operations are widely required in chemical vapor deposition, coating processes, etc. They increase scheduling complexity in cluster tools. In this paper, we focus on scheduling single-arm multi-cluster tools with chamber cleaning operations subject to wafer residency time constraints. When a chamber is being cleaned, it can be viewed as processing a virtual wafer. In this way, chamber cleaning operations can be performed while wafer residency time constraints for real wafers are not violated. Based on such a method, we present the necessary and sufficient conditions to analytically check whether a single-arm multi-cluster tool can be scheduled with a chamber cleaning operation and wafer residency time constraints. An algorithm is proposed to adjust the cycle time for a cleaning operation that lasts a long cleaning time.Meanwhile, algorithms for a feasible schedule are also derived.And an algorithm is presented for operating a multi-cluster tool back to a steady state after the cleaning. Illustrative examples are given to show the application and effectiveness of the proposed method.

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently,machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductormanufacturing.The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features.This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns.First,the number of defects during the actual process may be limited.Therefore,insufficient data are generated using convolutional auto-encoder(CAE),and the expanded data are verified using the evaluation technique of structural similarity index measure(SSIM).After extracting handcrafted features,a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction.Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns,the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.

Polynomial Approach to Optimal One-wafer Cyclic Scheduling of Treelike Hybrid Multi-Cluster Tools via Petri Nets

A treelike hybrid multi-cluster tool is composed of both single-arm and dual-arm cluster tools with a treelike topology. Scheduling such a tool is challenging. For a hybrid treelike multi-cluster tool whose bottleneck individual tool is process-bound, this work aims at finding its optimal one-wafer cyclic schedule. It is modeled with Petri nets such that a onewafer cyclic schedule is parameterized as its robots' waiting time.Based on the model, this work proves the existence of its onewafer cyclic schedule that features with the ease of industrial implementation. Then, computationally efficient algorithms are proposed to find the minimal cycle time and optimal onewafer cyclic schedule. Multi-cluster tool examples are given to illustrate the proposed approach. The use of the found schedules enables industrial multi-cluster tools to operate with their highest productivity.

Optimal Integrated Schedule of Entire Process of Dual-blade Multi-cluster Tools From Start-up to Close-down

Multi-cluster tools are widely used in majority of wafer fabrication processes in semiconductor industry. Smaller lot production, thinner circuit width in wafers, larger wafer size, and maintenance have resulted in a large quantity of their start-up and close-down transient periods. Yet, most of existing efforts have been concentrated on scheduling their steady states.Different from such efforts, this work schedules their transient and steady-state periods subject to wafer residency constraints. It gives the schedulability conditions for the steady-state scheduling of dual-blade robotic multi-cluster tools and a corresponding algorithm for finding an optimal schedule. Based on the robot synchronization conditions, a linear program is proposed to figure out an optimal schedule for a start-up period, which ensures a tool to enter the desired optimal steady state. Another linear program is proposed to find an optimal schedule for a closedown period that evolves from the steady state period. Finally,industrial cases are presented to illustrate how the provided method outperforms the existing approach in terms of system throughput improvement.

Cycle Time Analysis for Wafer Revisiting Process in Scheduling of Single-arm Cluster Tools

Some wafer fabrication processes performed by cluster tools require revisiting. With wafer revisiting, a cluster tool is very difficult to be scheduled due to a large number of possible schedules for the revisiting process. Atomic layer deposition （ALD） is a typical process with wafer revisiting that should be performed by cluster tools. This paper discusses the scheduling problem of single-arm cluster tools for the ALD process. In scheduling such a system, the most difficult part is to schedule the revisiting process such that the cycle time is minimized. Thus, this paper studies the revisiting process of ALD with revisiting times k = 3, 4, and 5, and analytical expressions are obtained to calculate the cycle time for the k possible schedules. Then, the schedule with the minimal cycle time is the optimal one. In this way, the scheduling problem of such a revisiting process becomes very simple and this is a significant improvement in scheduling cluster tools with wafer revisiting. Illustrative example is presented to show the application of the proposed method.

DTFab:A Digital Twin based Approach for Optimal Reticle Management in Semiconductor Photolithography

Photolithography is among the key phases in chip manufacturing.It is also among the most expensive with manufacturing equipment valued at the hundreds of millions of dollars.It is paramount that the process is ran efficiently,guaranteeing high resource utilization and low product cycle times.A key element in the operation of a photolithography system is the effective management of the reticles that are responsible for the imprinting of the circuit path on the wafers.Managing reticles means determining which are appropriate to mount on the very expensive scanners as a function of the product types being released to the system.Given the importance of the problem,several heuristic policies have been developed in the industry practice in an attempt to guarantee that the expensive tools are never idle.However,such policies have difficulties reacting to unforeseen events(e.g.,unplanned failures,unavailability of reticles).On the other hand,the technological advance of the semiconductor industry in sensing at system and process level should be harnessed to improve on these"expert policies".In this manuscript,we develop a system for the real time reticle management that not only is able to retrieve information from the real system,but also is able to embed commonly used policies to improve upon them.We develop a new digital twin for the photolithography process that efficiently and accurately predicts the system performance,thus allowing our system to make predictions for future behaviors as a function of possible decisions.Our results demonstrate the validity of the developed model,and the feasibility of the overall approach demonstrating a statistically significant improvement of performance as compared to the current policy.