A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM ...A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm^2.展开更多
High-speed,fixed-latency serial links find application in distributed data acquisition and control systems,such as the timing trigger and control(TTC)system for high energy physics experiments.However,most high-speed ...High-speed,fixed-latency serial links find application in distributed data acquisition and control systems,such as the timing trigger and control(TTC)system for high energy physics experiments.However,most high-speed serial transceivers do not keep the same chip latency after each power-up or reset,as there is no deterministic phase relationship between the transmitted and received clocks after each power-up.In this paper,we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays(FPGAs).First,we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver.Second,we use the internal alignment circuit of the transceiver and a digital clock manager(DCM)/phase-locked loop(PLL)based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver.The test results of the link latency are shown.Compared with existing solutions,our design not only implements fixed chip latency,but also reduces the average system lock time.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010403)the National Natural Science Foundation of China(No.60801045)
文摘A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm^2.
基金Project supported by the National Science and Technology Support Program of China(No.2012BAK24B01)the Fundamental Research Funds for the Central Universities,China(No.N100204001)+1 种基金the Specialized Research Fund for the Doctoral Program of Higher Edu-cation,China(No.20110042110021)the National Science Foundation for Post-doctoral Scientists of China(No.2013M541243)
文摘High-speed,fixed-latency serial links find application in distributed data acquisition and control systems,such as the timing trigger and control(TTC)system for high energy physics experiments.However,most high-speed serial transceivers do not keep the same chip latency after each power-up or reset,as there is no deterministic phase relationship between the transmitted and received clocks after each power-up.In this paper,we propose a fixed-latency serial link based on high-speed transceivers embedded in Xilinx field programmable gate arrays(FPGAs).First,we modify the configuration and clock distribution of the transceiver to eliminate the phase difference between the clock domains in the transmitter/receiver.Second,we use the internal alignment circuit of the transceiver and a digital clock manager(DCM)/phase-locked loop(PLL)based clock generator to eliminate the phase difference between the clock domains in the transmitter and receiver.The test results of the link latency are shown.Compared with existing solutions,our design not only implements fixed chip latency,but also reduces the average system lock time.
