This paper presents a serial synchronous scanning mode in fiat panel display （FPD） by adding a latch buffer between the serializer and the driving buffer. Comparing with conventional techniques, the proposed structu...This paper presents a serial synchronous scanning mode in fiat panel display （FPD） by adding a latch buffer between the serializer and the driving buffer. Comparing with conventional techniques, the proposed structure can efficiently reduce the brightness loss and improve the transmission performance. Theoretical analysis and experimental results show that the ratio between the lightest weight display time and the relative transmission time is a tradeoff between brightness loss and transmission efficiency.展开更多
Buffer influences the performance of production lines greatly.To solve the buffer allocation problem(BAP) in serial production lines with unreliable machines effectively,an optimization method is proposed based on an ...Buffer influences the performance of production lines greatly.To solve the buffer allocation problem(BAP) in serial production lines with unreliable machines effectively,an optimization method is proposed based on an improved ant colony optimization(IACO) algorithm.Firstly,a problem domain describing buffer allocation is structured.Then a mathematical programming model is established with an objective of maximizing throughput rate of the production line.On the basis of the descriptions mentioned above,combining with a two-opt strategy and an acceptance probability rule,an IACO algorithm is built to solve the BAP.Finally,the simulation experiments are designed to evaluate the proposed algorithm.The results indicate that the IACO algorithm is valid and practical.展开更多
The ordered event model is improved to describe serial production lines with limited buffer sizes. The improved model hasthe same computational burden as the original one and can be constrUcted directly according to g...The ordered event model is improved to describe serial production lines with limited buffer sizes. The improved model hasthe same computational burden as the original one and can be constrUcted directly according to given principles. Several simulationexamples are cited to verify this improved model. Extensions and open problems are also indicated. By means of this new model, serialProduotion lines with limitations of resources can be stUdied analytically.展开更多
In this paper, the efficiencies of two production lines, one is with commonly, the other is with separately buffer capacities are compared, the result is that the former one is better than the latter
In traditional universal asynchronous receiver transmitter （UART） controller, the data transmission is inefficient and the data bus utilization ratio is low. A novel design is provided to solve these problems. The a...In traditional universal asynchronous receiver transmitter （UART） controller, the data transmission is inefficient and the data bus utilization ratio is low. A novel design is provided to solve these problems. The architecture of the system is introduced, the flow charts of data processing as well as the implementation state machine are also presented in detail. This paper is concluded by comparing the performance of this design, which is realized on field programmable gate army （FPGA） using Verilog hardware description language （HDL）, with other traditional UART controllers.展开更多
A data acquisition system （DAS） to implement high-speed, real-time and multi-channel data acquisition and store is presented. The control of the system is implemented by the combination of complex programable logic ...A data acquisition system （DAS） to implement high-speed, real-time and multi-channel data acquisition and store is presented. The control of the system is implemented by the combination of complex programable logic device （CPLD） and digital signal processing （DSP）, the bulk buffer of the system is implemented by the combination of CPLD, DSP, and synchronous dynamic random access memory （SDRAM）, and the data transfer is implemented by the combination of DSP, first in first out （FIFO）, universal serial bus （USB） and USB hub. The system could not only work independently in single-channel mode, but also implement high-speed real-time multi-channel data acquisition system （MCDAS） by the combination of multiple single-channels. The sampling rate and data storage capacity of each channel could reach up to 100 million sampiing per second and 256 MB respectively.展开更多
基金Project supported by the Science Foundation of Shanghai Municipal Commission of Science and Technology （Grant Nos.055207041, 047062012）
文摘This paper presents a serial synchronous scanning mode in fiat panel display （FPD） by adding a latch buffer between the serializer and the driving buffer. Comparing with conventional techniques, the proposed structure can efficiently reduce the brightness loss and improve the transmission performance. Theoretical analysis and experimental results show that the ratio between the lightest weight display time and the relative transmission time is a tradeoff between brightness loss and transmission efficiency.
基金Supported by the National Natural Science Foundation of China(No.61273035,71471135)
文摘Buffer influences the performance of production lines greatly.To solve the buffer allocation problem(BAP) in serial production lines with unreliable machines effectively,an optimization method is proposed based on an improved ant colony optimization(IACO) algorithm.Firstly,a problem domain describing buffer allocation is structured.Then a mathematical programming model is established with an objective of maximizing throughput rate of the production line.On the basis of the descriptions mentioned above,combining with a two-opt strategy and an acceptance probability rule,an IACO algorithm is built to solve the BAP.Finally,the simulation experiments are designed to evaluate the proposed algorithm.The results indicate that the IACO algorithm is valid and practical.
文摘The ordered event model is improved to describe serial production lines with limited buffer sizes. The improved model hasthe same computational burden as the original one and can be constrUcted directly according to given principles. Several simulationexamples are cited to verify this improved model. Extensions and open problems are also indicated. By means of this new model, serialProduotion lines with limitations of resources can be stUdied analytically.
文摘In this paper, the efficiencies of two production lines, one is with commonly, the other is with separately buffer capacities are compared, the result is that the former one is better than the latter
基金National Natural Science Foundation of China (60532030)
文摘In traditional universal asynchronous receiver transmitter （UART） controller, the data transmission is inefficient and the data bus utilization ratio is low. A novel design is provided to solve these problems. The architecture of the system is introduced, the flow charts of data processing as well as the implementation state machine are also presented in detail. This paper is concluded by comparing the performance of this design, which is realized on field programmable gate army （FPGA） using Verilog hardware description language （HDL）, with other traditional UART controllers.
文摘A data acquisition system （DAS） to implement high-speed, real-time and multi-channel data acquisition and store is presented. The control of the system is implemented by the combination of complex programable logic device （CPLD） and digital signal processing （DSP）, the bulk buffer of the system is implemented by the combination of CPLD, DSP, and synchronous dynamic random access memory （SDRAM）, and the data transfer is implemented by the combination of DSP, first in first out （FIFO）, universal serial bus （USB） and USB hub. The system could not only work independently in single-channel mode, but also implement high-speed real-time multi-channel data acquisition system （MCDAS） by the combination of multiple single-channels. The sampling rate and data storage capacity of each channel could reach up to 100 million sampiing per second and 256 MB respectively.
