we investigate the effects of 60^Co γ-ray irradiation on the 130 nm partially-depleted silicon-on-isolator （PDSOI） input/output （I/O） n-MOSFETs. A shallow trench isolation （STI） parasitic transistor is responsi...we investigate the effects of 60^Co γ-ray irradiation on the 130 nm partially-depleted silicon-on-isolator （PDSOI） input/output （I/O） n-MOSFETs. A shallow trench isolation （STI） parasitic transistor is responsible for the observed hump in the back-gate transfer characteristic curve. The STI parasitic transistor, in which the trench oxide acts as the gate oxide, is sensitive to the radiation, and it introduces a new way to characterize the total ionizing dose （TID） responses in the STI oxide. A radiation enhanced drain induced barrier lower （DIBL） effect is observed in the STI parasitic transistor. It is manifested as the drain bias dependence of the radiation-induced off-state leakage and the increase of the DIBL parameter in the STI parasitic transistor after irradiation. Increasing the doping concentration in the whole body region or just near the STI sidewall can increase the threshold voltage of the STI parasitic transistor, and further reduce the radiation-induced off-state leakage. Moreover, we find that the radiation-induced trapped charge in the buried oxide leads to an obvious front-gate threshold voltage shift through the coupling effect. The high doping concentration in the body can effectively suppress the radiation-induced coupling effect.展开更多
The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all lea...The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage （Isub）, gate-induced-drain-leakage （/GIDL）, gate edge-direct-tunnelling leakage （IEDT） and band-to-band-tunnelling leakage （IBTBT） were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.展开更多
The effects of gamma irradiation on the shallow trench isolation（STI）leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold...The effects of gamma irradiation on the shallow trench isolation（STI）leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold voltage shift is negligible in all of the devices due to the very thin oxide thickness.However,an increase in the off-state leakage current is observed for all of the devices.We believe that the leakage is induced by the drain-to-source leakage path along the STI sidewall,which is formed by the positive trapped charge in the STI oxide.Also, we found that the leakage is dependent on the device＇s gate length.The three-transistor model（one main transistor with two parasitic transistors）can provide us with a brief understanding of the dependence on gate length.展开更多
The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide ...The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.展开更多
基于标准Bipolar-CMOS-DMOS(BCD)工艺研制的抗辐射电源管理芯片无法满足航天应用要求,抗辐射BCD工艺的发展严重制约了我国在航天领域核心器件的研制。与CMOS器件相比,LDMOS器件具有更高的工作电压和更多的介质结构,更易受到总剂量问题...基于标准Bipolar-CMOS-DMOS(BCD)工艺研制的抗辐射电源管理芯片无法满足航天应用要求,抗辐射BCD工艺的发展严重制约了我国在航天领域核心器件的研制。与CMOS器件相比,LDMOS器件具有更高的工作电压和更多的介质结构,更易受到总剂量问题的困扰。本文基于标准0.18μm BCD工艺,开展了18 V NLDMOS器件总剂量辐射效应研究,提出了一种总剂量辐射加固工艺技术。采用离子注入和材料改性技术工艺,提高了浅槽隔离场区边缘的P型硅反型阈值,从而增强了NLDMOS器件的抗辐射能力。通过对比实验表明,当辐照总剂量为100 krad(Si)时,加固的NLDMOS器件的抗辐射性能明显优于非加固的器件。通过总剂量辐射加固工艺技术的研究,可有效提高器件的抗总剂量辐射能力,避免设计加固造成芯片面积增大的问题。展开更多
基金supported by the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory,China(Grant No.ZHD201205)the National Natural Science Foundation of China(Grant No.61106103)
文摘we investigate the effects of 60^Co γ-ray irradiation on the 130 nm partially-depleted silicon-on-isolator （PDSOI） input/output （I/O） n-MOSFETs. A shallow trench isolation （STI） parasitic transistor is responsible for the observed hump in the back-gate transfer characteristic curve. The STI parasitic transistor, in which the trench oxide acts as the gate oxide, is sensitive to the radiation, and it introduces a new way to characterize the total ionizing dose （TID） responses in the STI oxide. A radiation enhanced drain induced barrier lower （DIBL） effect is observed in the STI parasitic transistor. It is manifested as the drain bias dependence of the radiation-induced off-state leakage and the increase of the DIBL parameter in the STI parasitic transistor after irradiation. Increasing the doping concentration in the whole body region or just near the STI sidewall can increase the threshold voltage of the STI parasitic transistor, and further reduce the radiation-induced off-state leakage. Moreover, we find that the radiation-induced trapped charge in the buried oxide leads to an obvious front-gate threshold voltage shift through the coupling effect. The high doping concentration in the body can effectively suppress the radiation-induced coupling effect.
文摘The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage （Isub）, gate-induced-drain-leakage （/GIDL）, gate edge-direct-tunnelling leakage （IEDT） and band-to-band-tunnelling leakage （IBTBT） were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.
文摘The effects of gamma irradiation on the shallow trench isolation（STI）leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold voltage shift is negligible in all of the devices due to the very thin oxide thickness.However,an increase in the off-state leakage current is observed for all of the devices.We believe that the leakage is induced by the drain-to-source leakage path along the STI sidewall,which is formed by the positive trapped charge in the STI oxide.Also, we found that the leakage is dependent on the device＇s gate length.The three-transistor model（one main transistor with two parasitic transistors）can provide us with a brief understanding of the dependence on gate length.
文摘The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.
文摘基于标准Bipolar-CMOS-DMOS(BCD)工艺研制的抗辐射电源管理芯片无法满足航天应用要求,抗辐射BCD工艺的发展严重制约了我国在航天领域核心器件的研制。与CMOS器件相比,LDMOS器件具有更高的工作电压和更多的介质结构,更易受到总剂量问题的困扰。本文基于标准0.18μm BCD工艺,开展了18 V NLDMOS器件总剂量辐射效应研究,提出了一种总剂量辐射加固工艺技术。采用离子注入和材料改性技术工艺,提高了浅槽隔离场区边缘的P型硅反型阈值,从而增强了NLDMOS器件的抗辐射能力。通过对比实验表明,当辐照总剂量为100 krad(Si)时,加固的NLDMOS器件的抗辐射性能明显优于非加固的器件。通过总剂量辐射加固工艺技术的研究,可有效提高器件的抗总剂量辐射能力,避免设计加固造成芯片面积增大的问题。
