test252 kV三相机械联动GIS用断路器的T100s合并试验

交流高压断路器标准GB/T 1984—2014中规定了中性点有效和非有效接地系统的合并试验,但是不涉及60Hz的工况,对应STL导则中针对IEC 62271-100有50/60Hz合并试验的描述,但是国内厂家50/60Hz通常是分开试验的。文章通过介绍252kV断路器T100s的多参数的合并试验,提供了一种可以多参数试验的试验方法,指出了多参数合并试验的利弊,对后续其他类似多参数合并试验提供了有效参考。

A Radial Stub Test Circuit for Microwave Power Devices

With the principles of microwave circuits and semiconductor device physics, two microwave power device test circuits combined with a test fixture are designed and simulated, whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz. The simulation and experimental results verify that the test circuit with a radial stub is better than that without. As an example, a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture. With a 5.4GHz microwave input signal,the maximum gain is 8.75dB,and the maximum output power is 33.2dBm.

The Transformer Short-Circuit Test and the High Power Laboratory in China-the Past,Present,and Future

We review the short-circuit testing of distribution and power transformers, and include a list of 110-220kV power transformers tested up to February 2002.

Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements.

Research on the overload protection reliability of moulded case circuit-breakers and its test device

This paper analyzed the reliability and put forward the reliability index of overload protection for moulded case circuit breaker. The success rate was adopted as its reliability index of overload protection. Based on the reliability index and the reli- ability level, the reliability examination plan was analyzed and a test device for the overload protection of moulded case cir- cuit-breaker was developed. In the reliability test of overload protection, two power sources were used, which reduced the time of conversion and regulation between two different test currents in the overload protection test, which made the characteristic test more accurate. The test device was designed on the base of a Windows system, which made its operation simple and friendly.

Key stress extraction and equivalent test method for hybrid DC circuit breaker

Firstly, relevant stress properties of millisecond level breaking process and microsecond level commutation process of hybrid HVDC circuit breaker are studied in detail on the basis of the analysis for the application environment and topological structure and operating principles of hybrid circuit breakers, and key stress parameters in transient state process of two time dimensions are extracted. The established digital simulation circuit for PSCAD/EMTDC device-level operation of the circuit breaker has verified the stress properties of millisecond level breaking process and microsecond level commutation process. Then, equivalent test method, circuits and parameters based on LC power supply are proposed on the basis of stress extraction. Finally, the results of implemented breaking tests for complete 200 kV circuit breaker, 100 kV and 50 kV circuit breaker units, as well as single power electronic module have verified the accuracy of the simulation circuit and mathematical analysis. The result of this paper can be a guide to electrical structure and test system design of hybrid HVDC circuit breaker.

Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.

Investigation into Equivalency of Synthetic Test Circuit Used for Operational Tests of Thyristor Valves for UHVDC

With the growth of capacity of high voltage direct current(HVDC) transmission lines,the ratings of thyristor valves,which are one of the most critical equipments,are getting higher and higher.Verification of performance of thyristor valves particularly designed for HVDC project plays an important role in the handover of products between the manufacturer and the client.Conventional test facilities based on philosophy of direct test cannot meet the requirements for modern thyristor valves.New test facilities with high ratings are necessarily built based on philosophy of synthetic test.Over the conventional direct test circuit,the later is an economical and feasible solution with less financial investment and higher test capability.However,the equivalency between the synthetic test and the direct test should be analyzed technically in order to make sure that the condition of verification test in a synthetic test circuit should satisfy the actual operation condition of thyristor valves existing in a real HVDC project,just as in a direct test circuit.Equivalency analysis is focused in this paper,covering the scope of thyristor valves' steady state,and transient state.On the basis of the results achieved,a synthetic test circuit of 6 500 A/50 kV for operational tests of thyristor valves used for up to UHVDC project has newly been set up and already put into service in Xi'an High Voltage Apparatus Research Institute Co.,Ltd.(XIHARI),China.Some of the results have been adopted also by a new national standard of China.

Research of the test generation algorithm based on search state dominance for combinational circuit

On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation.

The structure-based multi-fault test generation algorithm for combinational circuit

In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%.

VST/DL Digital Circuit Testing & Analytical System

An important means for digital circuit analysis, design. maintenance and production is the IC chip test and analysis. With digital circuit application prevailing today, the automatic test and analysis of digital circuits is going to play a more important role. It can save a great deal of time and cost for the maintenance of equipment and can also provide correst analytical data for designers.

A new approach to test generation for combinational circuits

Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits （CC） based on the chaotic particle swarm optimization （CPSO） algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS＇ 85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected fauhs.with original test vector, and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective.

The embedded design verification test of microwave circuit modules based on specific chips

In the Paper,the author introduces an embedded design verification test based on specific chips to solve the technical problems of microwave circuit test and fault diagnosis.The author explains embedded design of microwave circuit modules and approach of hardware design and software design,and finally verifies the embedded design of microwave circuit modules based on specific chips.

Chair's Introduction to 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis

Based on the recommendation of ICTD＇09 TPC members, this Special Issue of the Journal of Electronic Science ＆ Technology of China （JESTC） contained 22 high quality papers selected from the Proceedings of 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis （ICTD ＇09） which is fully sponsored by the IEEE Circuits and Systems Society （CASS）, and is technically co-sponsored by the University of Electronic Science and Technology of China （UESTC）, the Chinese Institute of Electronics （CIE）, the China Instrument ＆ Control Society （CIS）, and organized by UESTC.

基于加速退化试验的漏电信号调理电路性能退化及可靠性研究

在电子电路服役过程中,元器件退化会引起电路输出特性变化,降低电子电路的可靠性。漏电信号调理电路作为一种电子电路,其可靠性直接决定了漏电断路器的可靠性。以漏电信号调理电路为研究对象,首先基于灵敏度分析方法确定影响电路性能退化的关键元器件,并对漏电信号调理电路进行了以温度为加速应力、动作电流值为退化特征量的恒定应力加速退化试验;其次根据不同温度应力下的试验数据建立基于Wiener过程的漏电信号调理电路性能退化模型,并利用极大似然估计法求取退化模型的未知参数,进而得出寿命预测的概率密度函数和可靠度函数;最后利用阿伦尼斯(Arrhenius)方程外推出正常应力下漏电信号调理电路的预测寿命。相关结论可为不同电子电路的寿命预测及可靠度分析提供支撑。

针刺诱发电池热失控的研究进展综述

针刺测试是研究锂离子电池热失效机理和热失控特性的重要方法之一。本文汇总了目前广泛采用的针刺测试设置,并研究了不同变量对热失控演化的影响,包括针刺的深度、速度、位置以及针的材料和直径等,对针刺破坏下锂离子电池内短路及热失控行为进行机理性探索与分析。结果发现,针刺的深度与电池热失控行为的严重程度成正比,针刺的速度对电池热失控没有明显影响,针刺发生在活性材料较密集或电极附近时电池热失控更严重。针的材料和直径对电池热失控行为具有双重影响,需要结合实际情况对产热和散热情况分别进行分析。最后通过总结不同因素对电池热失控的影响,对减缓锂离子电池热失控以及更新其安全测试程序提出了新的见解,为后续的创新型研究工作提供思路。

重载水平多关节装卸机器人设计与研究

文章针对安装高度空间有限的重型货物搬运问题,设计了一种重载水平多关节装卸机器人。为减小高度空间占用,该机器人结构采用大臂小臂等高串联的形式和钢丝绳卷扬形式的升降轴;为扩大小臂的回转范围,设置了随动传动机构的辅助臂。同时,对装卸机器人的控制系统进行了设计,并根据不同极限工况下的受载情况,对整机进行了有限元分析。结果表明,最大应力发生在工况一时辅助臂上,最大值为199.8MPa。最大变形量发生在工况一时,节点最大综合位移为35mm,机器人结构设计合理。

工业电子雷管在拆除爆破中的应用

近年来,工业电子雷管的产量总体保持高速增长,主要应用于露天土岩和隧道掘进爆破领域,在拆除爆破领域的使用量不足5%。为分析工业电子雷管在拆除爆破应用过程中存在的问题,结合拆除爆破工程案例,发现逐发扫描录入雷管的效率较低,需提高工业电子雷管起爆系统单台起爆器的起爆能以及扫描录入雷管和连接卡扣的效率。结合大规模工业电子雷管起爆网路试验,发现工业电子雷管起爆网路的传爆可靠性较高,雷管的报错率为0.03%~0.07%,拒爆率为0.02%;通过扫描盒条码录入雷管,可显著提高连网的操作工效。在拆除爆破工程中,需要根据结构的倒塌运动过程合理设置构件的起爆时间,根据工程规模定制合适的盒包装雷管数量,从而提高工业电子雷管起爆网路的适用性。

模拟短路试验核对变电所保护极性的方法探讨

近几年,因保护回路接线错误造成保护拒动、误动的事件频发。通过实际案例,从理论、实际多角度分析故障发生的原因,提出一种新型短路试验方法,并应用于实际验证其可靠性,以期为变配电设备运维、新线开通提供参考。

高温气冷堆热态功能试验中一回路加热动态特性研究

高温气冷堆反应堆压力容器堆内构件由石墨和碳化硼烧结陶瓷材料组成,热态功能试验过程中需对一回路堆内构件进行加热除湿。针对高温气冷堆一回路热试系统特点,采用COMSOL Multiphysics 5.4计算软件构建了压力容器、蒸汽发生器和主氦风机三维数值模型,并通过示范工程加热试验值验证了模型的可靠性,并获得了一回路加热过程中温度场动态特性。为了解决高温气冷堆示范工程一回路首次加热效率低的问题,提出了将辅助蒸汽通入到蒸汽发生器,并动态调整辅助蒸汽运行参数来加热一回路氦气的方法,结果表明:相较于主氦风机单独加热方式,外加辅助蒸汽热源可节省加热时间约31.3 h,同时可将堆芯最终平衡温度由250℃提高至265℃;在满足运行准则的前提下,更有利于碳砖和石墨堆内构件的除湿。该研究结果为高温气冷堆一回路热试提供了有力支持。