基于最小有功注入策略,提出一种新型的动态电压恢复器(dynamic voltage restorer,DVR)结构,其主要结构由基本的级联H桥逆变器和并联的晶闸管开关电感组成。文章分析了新型DVR的电路拓扑和基本原理,推导了最小有功注入策略,分析了DVR的...基于最小有功注入策略,提出一种新型的动态电压恢复器(dynamic voltage restorer,DVR)结构,其主要结构由基本的级联H桥逆变器和并联的晶闸管开关电感组成。文章分析了新型DVR的电路拓扑和基本原理,推导了最小有功注入策略,分析了DVR的补偿能力和负载功率因数的关系,并设计了合适的控制系统。仿真结果表明,新型DVR可以处理更严重和更长时间的电压跌落,大大减少了DVR的有功注入。展开更多
A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impe...A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.展开更多
Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat...Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.展开更多
An all-transistor active-inductor shunt-peaking structure has been used in a prototype of 8 Gbps high- speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL dri...An all-transistor active-inductor shunt-peaking structure has been used in a prototype of 8 Gbps high- speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25 p^m Silicon-on-Sapphire （SOS） CMOS process for radiation tolerant purpose. The all-transistor active-inductor shunt-peaking is used to overcome the bandwidth limitation from the CMOS pro- cess. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been taped out, and the prototype has been proven by the preliminary electrical test results and bit error ratio test results. The driver achieves 8 Gbps data rate as simulated with the peaking. We present the all-transistor active-inductor shunt-peaking structure, simulation and test results in this paper.展开更多
文摘基于最小有功注入策略,提出一种新型的动态电压恢复器(dynamic voltage restorer,DVR)结构,其主要结构由基本的级联H桥逆变器和并联的晶闸管开关电感组成。文章分析了新型DVR的电路拓扑和基本原理,推导了最小有功注入策略,分析了DVR的补偿能力和负载功率因数的关系,并设计了合适的控制系统。仿真结果表明,新型DVR可以处理更严重和更长时间的电压跌落,大大减少了DVR的有功注入。
基金Supported by the National Natural Science Foundation of China(No.61474081)
文摘A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18 μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transimpedance of 60.5 d B?, and a-3 d B bandwidth of 5.4 GHz is achieved for 0.5 p F input capacitance. The average equivalent input noise current spectral density is about 20 p A/Hz^(1/2) in the interested frequency, and the TIA consumes 20 m W DC power under 1.8 V supply voltage. The voltage swing is 460 m V pp, and the saturation input current is 500 μA.
文摘Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.
基金Supported by National Natural Science Foundation of China(11075152)
文摘An all-transistor active-inductor shunt-peaking structure has been used in a prototype of 8 Gbps high- speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25 p^m Silicon-on-Sapphire （SOS） CMOS process for radiation tolerant purpose. The all-transistor active-inductor shunt-peaking is used to overcome the bandwidth limitation from the CMOS pro- cess. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been taped out, and the prototype has been proven by the preliminary electrical test results and bit error ratio test results. The driver achieves 8 Gbps data rate as simulated with the peaking. We present the all-transistor active-inductor shunt-peaking structure, simulation and test results in this paper.
