A new analytical model of high voltage silicon on insulator(SOI) thin film devices

A new analytical model of high voltage silicon on insulator （SOI） thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon fihn thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30 V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage （VB,V） are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2 μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.

THE GROWTH OF MONOCRYSTALLINE SILICON THIN FILM ON INSULATOR (SOI) BY SCANNING ELECTRON BEAM

An experiment for preparation of SOI films by using the scanning electron beam to modify the polycrystalline silicon on SiO2 is presented. This method takes on the epitaxial lateral growth of liquid phase with the crystallon to form monocrystalline silicon films. The effects of the beam power density, scanning velocity, temperature of the substrates and the construction of samples on the quality of the monocrystalline silicon films were discussed. A good experimental result has been obtained, the monocrystalline silicon zone is nearly 200×25μm2.

Estimation of pulsed laser-induced single event transient in a partially depleted silicon-on-insulator 0.18-μm MOSFET

In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.

Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors

The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.

Analytical base collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector- base bias-and shows a kink as the reverse collector-base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.

Study on the defect-related emissions in the light self-ion-implanted Si films by a silicon-on-insulator structure

This paper reports that the Si＋ self-ion-implantation are conducted on the silicon-on-insulator wafers with the 2SSi＋ doses of 7 ×1012, 1 × 1013, 4 × 1013, and 3× 1014 cm-2, respectively. After the suitable annealing, these samples are characterized by using the photoluminescence technique at different recorded temperatures. Plentiful emission peaks are observed in these implanted silicon-on-insulator samples, including the unwonted intense P~ band which exhibits a great potential in the optoelectronic application. These results indicate that severe transformation of the interstitial clusters can be manipulated by the implanting dose at suitable annealing temperatures. The high critical temperatures for the photoluminescence intensity growth of the two signatures are well discussed based on the thermal ionization model of free exciton.

Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.

Total dose radiation response of modified commercial silicon-on-insulator materials with nitrogen implanted buried oxide

Nitrogen ions of various doses are implanted into the buried oxide （BOX） of commercial silicon-on-insulator （SOI） materials, and subsequent annealings are carried out at various temperatures. The total dose radiation responses of the nitrogen-implanted SOI wafers are characterized by the high frequency capacitance-voltage （C-V） technique after irradi- ation using a Co-60 source. It is found that there exist relatively complex relationships between the radiation hardness of the nitrogen implanted BOX and the nitrogen implantation dose at different irradiation doses. The experimental results also suggest that a lower dose nitrogen implantation and a higher post-implantation annealing temperature are suitable for improving the radiation hardness of SOI wafer. Based on the measured C V data, secondary ion mass spectrometry （SIMS）, and Fourier transform infrared （FTIR） spectroscopy, the total dose responses of the nitrogen-implanted SOI wafers are discussed.

An analytical model for coplanar waveguide on silicon-on-insulator substrate with conformal mapping technique

In this paper, the authors present an analytical model for coplanar waveguide on silicon-on-insulator substrate. The four-element topological network and the conformal mapping technique are used to analyse the capacitance and the conductance of the sandwich substrate. The validity of the model is verified by the full-wave method and the experimental data. It is found that the inductance, the resistance, the capacitance and the conductance from the analytical model show they are in good agreement with the corresponding values extracted from experimental Sparameter until 10 GHz.

SDB-SOI制备过程中工艺控制

SOI(Silicom-On-Insulator)晶圆是绝缘氧化物上有一层薄硅膜的硅晶圆。在SDB-SOI晶圆制备过程中,需要在进行晶圆键合、磨削、抛光等工序过程中,通过对键合空腔、顶硅厚度、顶硅TTV、顶硅形状、顶硅表面等参数的控制,可以降低后续工序加工难度,最终制备出高质量的产品。

Influence of nitrogen implantation into the buried oxide on the radiation hardness of silicon-on-insulator wafers

In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon- on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 1016 cm-2, and subsequent annealing was performed at 1100 ℃. The effect of annealing time on the radiation hardness of the nitrogen implanted wafers has been studied by the high frequency capacitance-voltage technique. The results suggest that the improvement of the radiation hardness of the wafers can be achieved through a shorter time annealing after nitrogen implantation. The nitrogen-implanted sample with the shortest annealing time 0.5 h shows the highest tolerance to total-dose radiation. In particular, for the 1.0 and 1.5 h annealing samples, both total dose responses were unusual. After 300-krad（Si） irradiation, both the shifts of capacitance-voltage curve reached a maximum, respectively, and then decreased with increasing total dose. In addition, the wafers were analysed by the Fourier transform infrared spectroscopy technique, and some useful results have been obtained.

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium （SiGe） heterojunction bipolar transistor （HBT） on thin silicon-on-insulator （SOI） has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base-collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiCe devices and circuits.

Analysis and Simulation of S-shaped Waveguide in Silicon-on-insulator

The simulation and analysis of S-shaped waveguide bend are presented.Bend radius larger than 30 mm assures less than 0.5 dB radiation loss for a 4-μm-wide silicon-on-insulator waveguide bend with 2-μm etch depth.Intersection angle greater than 20° provides negligible crosstalk (<-30 dB) and very low insertion loss.Any reduction in bend radius and intersection angle is at the cost of the degradation of characteristics of bent waveguide and intersecting waveguide, respectively.

Design and Fabrication of MEMS Gyroscopes on the Silicon-on-insulator Substrate with Decoupled Oscillation Modes

The mode coupling is a major factor to affect the precision of the micro electromechanical systems（MEMS） gyroscope. Currently, many MEMS gyroscopes with separate oscillation modes for drive and detection have been developed to decrease the mode coupling, but the gyroscope accuracy can not satisfy the high-precision demand well. Therefore, high performance decoupled MEMS gyroscopes is still a hot topic at present. An innovative design scheme for a MEMS gyroscope is designed, and in this design, the inertial mass is divided into three parts including the inner mass, the outer mass and the main frame mass. The masses are supported and separated by a set of mutually orthogonal beams to decouple their movements. Moreover, the design is modelled by multi-port-element network（MuPEN） method and the simulation results show that the mode coupling of the gyroscope between driving and sensing mode was eliminated effectively. Furthermore, we proposed a new silicon-on-insulator（SOI） process to fabricate the gyroscope. The scale factor of the fabricated gyroscope is 8.9 mV/（（~）os） and the quality factor（Q-factor） is as high as 600 at atmosphere pressure, and then, the resonant frequency, scale factor and bias drift has been test. Process and test results show that the proposed MEMS gyroscope are effective for decrease mode coupling, furthermore, it can achieve a high performance at atmosphere pressure. Furthermore, the MEMS gyroscope can achieve a high performance at atmosphere pressure. The research can be taken as good advice for the design and fabrication of MEMS gyroscope, meanwhile, it also provides technical support for speeding up of MEMS gyroscope industrialization.

Improvement of total-dose irradiation hardness of silicon-on-insulator materials by modifying the buried oxide layer with ion implantation

The hardening of the buried oxide （BOX） layer of separation by implanted oxygen （SIMOX） silicon-on-insulator （SOI） wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad（SiO2）. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.