具有缺弧和失效点的单定向超立方体的诊断度

对于大规模多处理器系统,为了保证其可靠性,需要将发生故障的处理器及时诊断出来并进行更换。诊断度是系统能够自我识别的故障处理器的最大数目。n维单定向超立方体UQ_(n)是通过对超立方体Q_(n)所有的边进行定向得到的一个有向网络。研究了PMC模型下具有缺弧和失效点的单定向超立方体的诊断度。设S是UQ_(n)中缺弧和失效点的集合且S≤n/2」-1.通过对其缺弧和失效点的分布模式进行讨论,得到了UQ_(n)-S在PMC模型下的诊断度为UQ_(n)-S的最小入度,其中n≥3.

An Efficient Real-Time Fault-Tolerant Scheduling Algorithm Based on Multiprocessor Systems

In the context of real-time fault-tolerant scheduling in multiprocessor systems, Primary-backup scheme plays an important role. A backup copy is always preferred to be executed as passive backup copy whenever possible because it can take the advantages of backup copy de-allocation technique and overloading technique to improve schedulability. In this paper, we propose a novel efficient fault-tolerant ratemonotonic best-fit algorithm efficient fault-tolerant rate-monotonic best-fit （ERMBF） based on multiprocessors systems to enhance the schedulability. Unlike existing scheduling algorithms that start scheduling tasks with only one processor. ERMBF pre-allocates a certain amount of processors before starting scheduling tasks, which enlarge the searching spaces for tasks. Besides, when a new processor is allocated, we reassign the task copies that have already been assigned to the existing processors in order to find a superior tasks assignment configuration. These two strategies are all aiming at making as many backup copies as possible to be executed as passive status. As a result, ERMBF can use fewer processors to schedule a set of tasks without losing real-time and fault-tolerant capabilities of the system. Simulation results reveal that ERMBF significantly improves the schedulability over existing, comparable algorithms in literature.

Development of FPGA Based NURBS Interpolator and Motion Controller with Multiprocessor Technique

The high-speed computational performance is gained at the cost of huge hardware resource,which restricts the application of high-accuracy algorithms because of the limited hardware cost in practical use.To solve the problem,a novel method for designing the field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller,which adopts the embedded multiprocessor technique,is proposed in this study.The hardware and software design for the multiprocessor,one of which is for NURBS interpolation and the other for position servo control,is presented.Performance analysis and experiments on an X-Y table are carried out,hardware cost as well as consuming time for interpolation and motion control is compared with the existing methods.The experimental and comparing results indicate that,compared with the existing methods,the proposed method can reduce the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms.A method which ensures the real-time performance and interpolation accuracy,and reduces the hardware cost significantly is proposed,and it’s practical in the use of industrial application.

Dynamic Load Balancing Based on Restricted Multicast Tree in Homogeneous Multiprocessor Systems

To decrease the cost of exchanging load information among processors, a dynamic load-balancing （DLB） algorithm which adopts multieast tree technology is proposed. The muhieast tree construction rules are also proposed to avoid wrongly transferred or redundant DLB messages due to the overlapping of multicast trees. The proposed DLB algorithm is distributed controlled, sender initiated and can help heavily loaded processors with complete distribution of redundant loads with minimum number of executions. Experiments were executed to compare the effects of the proposed DLB algorithm and other three ones, the results prove the effectivity and practicability of the proposed algorithm in dealing with great scale compute-intensive tasks.

Timed Petri Net Models of Shared-Memory Bus-Based Multiprocessors

In shared-memory bus-based multiprocessors, when the number of processors grows, the processors spend an increasing amount of time waiting for access to the bus (and shared memory). This contention reduces the performance of processors and imposes a limitation of the number of processors that can be used efficiently in bus-based systems. Since the multi-processor’s performance depends upon many parameters which affect the performance in different ways, timed Petri nets are used to model shared-memory bus-based multiprocessors at the instruction execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system. The results illustrate very well the restriction on the number of processors imposed by the shared bus. All performance characteristics presented in this paper are obtained by discrete-event simulation of Petri net models.

Approximation algorithm for multiprocessor parallel job scheduling

P k |fix| C max problem is a new scheduling problem based on the multiprocessor parallel job, and it is proved to be NP hard problem when k ≥3. This paper focuses on the case of k =3. Some new observations and new techniques for P 3 |fix| C max problem are offered. The concept of semi normal schedulings is introduced, and a very simple linear time algorithm Semi normal Algorithm for constructing semi normal schedulings is developed. With the method of the classical Graham List Scheduling, a thorough analysis of the optimal scheduling on a special instance is provided, which shows that the algorithm is an approximation algorithm of ratio of 9/8 for any instance of P 3|fix| C max problem, and improves the previous best ratio of 7/6 by M.X.Goemans.

Development of single-chip fuzzy controller based on FFSI in binary

Length and concise structure of fuzzy logic reasoning program and its real-time reasoning characteris-tic have their effect on the performance of a digital single-chip fuzzy controller. The control effect of a digitalfuzzy controller based on looking up fuzzy control responding table is only relative to the table and not relative tothe fuzzy control rules in the practical control process. Aiming at above problem and having combined fuzzy log-ic reasoning with digital operational characteristics of a single-chip microcomputer, functioning-fuzzy-subset in-ference (FFSI) in binary, in which triangle membership functions of error and error-in-change are all represen-ted in binary and singleton membership functions of control variable is binary too, has been introduced. The cir-cuit principle plans of a single-chip fuzzy controller have been introduced for development of its hardware, andthe primary program structure, fuzzy logic reasoning subroutine, serial communication subroutine with PC andreliability design of the fuzzy controller are all discussed in detail. The control of indoor temperature by a fuzzycontroller has been conducted using a testing-room thermodynamic system. Research results show that the FFSIin binary can exercise a concise fuzzy control in a single-chip fuzzy controller, and the fuzzy controller is there-fore reliable and possesses a high performance-price ratio.

Fork-Join program response time on multiprocessors with exchangeable join

The Fork-Join program consisting of K parallel tasks is a useful model for a large number of computing applications. When the parallel processor has multi-channels, later tasks may finish execution earlier than their earlier tasks and may join with tasks from other programs. This phenomenon is called exchangeable join (EJ), which introduces correlation to the task’s service time. In this work, we investigate the response time of multiprocessor systems with EJ with a new approach. We analyze two aspects of this kind of systems: exchangeable join (EJ) and the capacity constraint (CC). We prove that the system response time can be effectively reduced by EJ, while the reduced amount is constrained by the capacity of the multiprocessor. An upper bound model is constructed based on this analysis and a quick estimation algorithm is proposed. The approximation formula is verified by extensive simulation results, which show that the relative error of approximation is less than 5%.

Gas concentration monitoring system for small and medium-sized coal mines based on gas-sensing detection and single-chip control

This paper is aimed at the actual conditions of disaster caused by gas in small and medium-sized coal mines. A new gas concentration monitoring system for coal mines is developed on the basis of gas-sensing detection and single-chip control. The monitoring system uses the tin oxide as the main material of N-type semiconductor gas sensors, be- cause it has good sensitive characteristics for the flammable and explosive gas （ such as methane, carbon monoxide）. The QM-N5-semiconductor gas sensor is adopted to detect the output values of the resistance under the different gas con- centrations. The system, designedly, takes the AT89C51 digital chip as the core of the circuit processing hardware structure to analyze and judge the input values of the resistance, and then achieve the control and alarm for going beyond the limit of gas concentration. The gas concentration monitoring system has man）, advantages including simple in struc- ture, fast response time, stable performance and low cost. Thus, it can be widely used to monitor gas concentration and provide early wamings in small and medium-sized coal mines.

Study and Analysis of Bus Arbitration Mechanism in PI-MPS Multiprocessor System

This paper presents the mechanism of the bus arbitration in PI-MPS multiprocessor sys-tem,describes encode approach,arbiter timing states and uniqueness of master modular ininterconnection bus,and measures and analyses latency of bus arbitration as well.

Design of efficient parallel algorithms on shared memory multiprocessors

The design of parallel algorithms is studied in this paper. These algorithms are applicable to shared memory MIMD machines In this paper, the emphasis is put on the methods for design of the efficient parallel algorithms. The design of efficient parallel algorithms should be based on the following considerationst algorithm parallelism and the hardware-parallelism; granularity of the parallel algorithm, algorithm optimization according to the underling parallel machine. In this paper , these principles are applied to solve a model problem of the PDE. The speedup of the new method is high. The results were tested and evaluated on a shared memory MIMD machine. The practical results were agree with the predicted performance.

A Particle Swarm Optimization to Minimize Makespan for a Four-Stage Multiprocessor Open Shop with Dynamic Job Release Time

This paper considers the scheduling problem observed in chip sorting operation of LED manufacturing, where each lot (job) with release time have four operations to be processed on a set of processing stages without pre-determined necessary route. Each stage has one and more identical sorting machines. The sorting machines scheduling problem can be treated as a four-stage multiprocessor open shop problem with dynamic job release, and the objective is minimizing the makespan in the paper. This problem is formulated into a mixed integer programming (MIP) model and empirically shows its computational intractability. Due to the computational intractability, a particle swarm optimization (PSO) algorithm is proposed. A series of computational experiments are conducted to evaluate the performance of the proposed PSO in comparison with exact solution on various small-size problem instances. The results show that the PSO algorithm could finds most optimal or better solutions in one second.

YH-MCS Reconstructable Fault-tolerant Multiprocessor Control System

FMS is the basic and frontier technology of advanced manufacturing.Its critical compo-nent is FMS control system.Reconstructable fault-tolerant multiprocessor control system,YH-MCS,is the result of the research on the high-performance and high-reliable FMS con-trol system.This paper describes its architecture,technology characteristics,academic valueand application potentiality.

Temporal consistency maintenance on multiprocessor platforms with instance skipping

Maintaining temporal consistency of real-time data is important for cyber-physical systems.Most of the previous studies focus on uniprocessor systems.In this paper,the problem of temporal consistency maintenance on multiprocessor platforms with instance skipping was formulated based on the(m,k)-constrained model.A partitioned scheduling method SC-AD was proposed to solve the problem.SC-AD uses a derived sufficient schedulability condition to calculate the initial value of m for each sensor transaction.It then partitions the transactions among the processors in a balanced way.To further reduce the average relative invalid time of real-time data,SC-AD judiciously increases the values of m for transactions assigned to each processor.Experiment results show that SC-AD outperforms the baseline methods in terms of the average relative invalid time and the average valid ratio under different system workloads.

A Single-Chip UHF RFID Reader Transceiver IC

A single-chip UHF RFID reader transceiver IC has been implemented in 0.18 μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2C with fully-compliant China 800/900 MHz RFID draft, ISO/IEC 18000-6C protocol and ETSI 302 208-1 local regulation. The normal mode receiver in the presence of -3 dBm self-jammer achieves -75 dBm 1% PER sensitivity. The linear class-A PA integrated in transmitter has 25 dBm OP1 dB output power for CW. The fully-integrated fractional-N fre-quency synthesizer is designed based on MASH 1-1-1 sigma-delta modulator and 1.8 GHz fundamental frequency LC-VCO for lower in-band and out-of-band phase noise. The measured phase noise is up to -106 dBc/Hz@200 kHz and -131 dBc/Hz@1 MHz offset from center frequency and the integrated RMS jitter from 10 kHz to 10 MHz is less than 1.6 pS. The chip dissipates 330 mA from 3.3 V power supply when transmitting 22.4 dBm CW signal and the PAE of linear PA is up to 26%. The chip die area is 16.8 mm2.

互连网络连通度与诊断度的关联关系研究综述

连通度与诊断度不仅在定义上存在着紧密的关联关系,而且一些诊断度理论也是受到了相关连通度的启发而提出的.本文首先系统综述了连通度与诊断度的研究进展,重点梳理了连通度与诊断度的关联关系,得出了在多处理器计算机系统中,多种诊断度会随着相关连通度的提高而增强,同时呈现出明显线性关系的重要结论.进而通过研究,确定了诊断度与相关连通度之间的具体关联关系可以大大简化诊断度的度量过程,快速计算出多处理器计算机系统的各类诊断度.最后,提出了以互连网络为研究对象,未来开展连通度与诊断度的关联关系研究的方向.研究成果对于推进互连网络的可靠性研究、促进互连网络的应用推广有着非常重要的参考价值.

概率故障条件下k元(n-m)方体子网络的可靠性

k元n方体具有许多优良特性,已成为多处理器系统最常用的互连网络拓扑结构之一。当系统互连网络中发生故障时,系统子网络的保持能力对系统实际应用至关重要。为了精确度量k元n方体中任意规模子网络的容错能力,研究了有故障发生时k元n方体中k元(n-m)方体子网络的可靠性。当k(k≥3)为奇整数时,在概率故障条件下得出了k元n方体中存在无故障k元(n-m)方体子网络的概率的上界和下界,并给出了该可靠性的一种近似评估方法。实验结果表明,随着顶点可靠性的降低,k元(n-m)方体子网络可靠性的上下界趋于一致;当顶点可靠性较高时,利用近似评估方法得出的结果更为准确。

k元(n-1)方体子网络可靠性的近似评估方法

多处理器系统互连网络的拓扑性质对系统功能的实现起着重要的作用。k元n方体网络的子网络可靠性是以k元n方体为拓扑结构构建的多处理器系统处理计算任务时需要考虑的一个重要因素。为了精确高效地度量概率故障条件下k元n方体中k元(n-1)方体子网络的可靠性,提出基于反向传播(BP)神经网络的k元(n-1)方体子网络可靠性的近似评估方法。首先,利用蒙特卡洛仿真方法和k元(n-1)方体子网络可靠性的已有上下界给出用于训练BP神经网络的数据集的生成方法;其次,基于生成的训练数据集构造用于评估k元(n-1)方体子网络可靠性的BP神经网络模型;最后,对BP神经网络模型得出的k元(n-1)方体子网络可靠性的近似评估结果进行了分析,并与近似计算公式和基于蒙特卡洛的评估方法的结果进行了对比。与近似计算公式相比,所提方法得出的结果更为精确;与基于蒙特卡洛的评估方法相比,所提方法的评估耗时平均减少了约59%。实验结果表明,所提方法在兼顾精度和效率方面具有一定优势。