This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transac...This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transaction. Secondly it analyzes hardware snoopy mechanism of P6 bus and MESI state transitions adopted by Pentium Ⅲ. Based on these, it focuses on how muhiprocessors and the P6 bus cooperate to ensure cache coherency of the whole system, and gives the key of cache coherency design.展开更多
A method for automatic verification of cache coherence protocols is presented, in which cache coherence protocols are modeled as concurrent value-passing processes, and control and data consistency requirement are des...A method for automatic verification of cache coherence protocols is presented, in which cache coherence protocols are modeled as concurrent value-passing processes, and control and data consistency requirement are described as formulas in first-order p-calculus. A model checker is employed to check if the protocol under investigation satisfies the required properties. Using this method a data consistency error has been revealed in a well-known cache coherence protocol. The error has been corrected, and the revised protocol has been shown free from data consistency error for any data domain size, by appealing to data independence technique.展开更多
Directory protocols are widely adopted to maintain cache coherence of distributed shared memory multiprocessors. Although scalable to a certain extent, directory protocols are complex enough to prevent it from being u...Directory protocols are widely adopted to maintain cache coherence of distributed shared memory multiprocessors. Although scalable to a certain extent, directory protocols are complex enough to prevent it from being used in very large scale multiprocessors with tens of thousands of nodes. This paper proposes a lock-based cache coherence protocol for scope conyistency. It does not rely on directory information to maintain cache coherence. Instead, cache coherence is mailltained through requiring the releasing processor of a lock to store all write-notices generated in the associated critical section to the lock and the acquiring processor invalidates or updates its locally cached data copies according to the write notices of the lock. To evaluate the performance of the lock-based cache coherence protocol, a software DSM system named JIAJIA is built on network of workstations. Besides the lockbased cache coherence protocol, JIAJIA also characterizes itself with its shared memory organization scheme which combines the physical memories of multiple workstations to form a large shared space. Performance measurements with SPLASH2 program suite and NAS benchmarks indicate that, compared to recent SVM systems such as CVM, higher speedup is achieved by JIAJIA.Besides, JIAJIA can solve large scale problems that cannot be solved by other SVM systems due to memory size limitation.展开更多
提出一种利用月面月球车-着陆器UHF(Ultra High Frequency)近程通信链路的高精度测距、测角的新方法,实现月球车的精密定位.该体制采用直序扩频和CCSDS(Con-sultative Committee for Space Date Systems)Proximity-1协议实现月球车-着...提出一种利用月面月球车-着陆器UHF(Ultra High Frequency)近程通信链路的高精度测距、测角的新方法,实现月球车的精密定位.该体制采用直序扩频和CCSDS(Con-sultative Committee for Space Date Systems)Proximity-1协议实现月球车-着陆器之间的数据交互,利用双向异步传输帧非相干扩频测距方法实现精密测距,利用着陆器双天线形成短基线实现对月球车方位角的精密测量.讨论了用于测距的CCSDS Proximity-1协议帧结构、双向异步传输帧测距原理、方位角的载波相位差分干涉测量原理,以及建立月面着陆参考系并给出月球车精确定位的方法.研究表明,所提出的方法功能集成度高、信道资源利用率高、设备简单、性能指标满足月球探测二期月球车的月面定位、通信任务需求.展开更多
文摘This paper analyzes cache coherency mechanism from the view of system. It firstly discusses caehe-memory hierarchy of Pentium Ⅲ SMP system, including memory area distribution, cache attributes control and bus transaction. Secondly it analyzes hardware snoopy mechanism of P6 bus and MESI state transitions adopted by Pentium Ⅲ. Based on these, it focuses on how muhiprocessors and the P6 bus cooperate to ensure cache coherency of the whole system, and gives the key of cache coherency design.
基金Supported by the Intel Strategic CAD Labs, the National Natural Science Foundation of China （Grant No. 60421001）, and the Chinese Academy of Sciences.
文摘A method for automatic verification of cache coherence protocols is presented, in which cache coherence protocols are modeled as concurrent value-passing processes, and control and data consistency requirement are described as formulas in first-order p-calculus. A model checker is employed to check if the protocol under investigation satisfies the required properties. Using this method a data consistency error has been revealed in a well-known cache coherence protocol. The error has been corrected, and the revised protocol has been shown free from data consistency error for any data domain size, by appealing to data independence technique.
文摘Directory protocols are widely adopted to maintain cache coherence of distributed shared memory multiprocessors. Although scalable to a certain extent, directory protocols are complex enough to prevent it from being used in very large scale multiprocessors with tens of thousands of nodes. This paper proposes a lock-based cache coherence protocol for scope conyistency. It does not rely on directory information to maintain cache coherence. Instead, cache coherence is mailltained through requiring the releasing processor of a lock to store all write-notices generated in the associated critical section to the lock and the acquiring processor invalidates or updates its locally cached data copies according to the write notices of the lock. To evaluate the performance of the lock-based cache coherence protocol, a software DSM system named JIAJIA is built on network of workstations. Besides the lockbased cache coherence protocol, JIAJIA also characterizes itself with its shared memory organization scheme which combines the physical memories of multiple workstations to form a large shared space. Performance measurements with SPLASH2 program suite and NAS benchmarks indicate that, compared to recent SVM systems such as CVM, higher speedup is achieved by JIAJIA.Besides, JIAJIA can solve large scale problems that cannot be solved by other SVM systems due to memory size limitation.
文摘提出一种利用月面月球车-着陆器UHF(Ultra High Frequency)近程通信链路的高精度测距、测角的新方法,实现月球车的精密定位.该体制采用直序扩频和CCSDS(Con-sultative Committee for Space Date Systems)Proximity-1协议实现月球车-着陆器之间的数据交互,利用双向异步传输帧非相干扩频测距方法实现精密测距,利用着陆器双天线形成短基线实现对月球车方位角的精密测量.讨论了用于测距的CCSDS Proximity-1协议帧结构、双向异步传输帧测距原理、方位角的载波相位差分干涉测量原理,以及建立月面着陆参考系并给出月球车精确定位的方法.研究表明,所提出的方法功能集成度高、信道资源利用率高、设备简单、性能指标满足月球探测二期月球车的月面定位、通信任务需求.
