Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System

In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.

Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

A hardware/software co-optimization approach for embedded software of MP3 decoder

In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction

We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.

Research on Software Radio Fuze

The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kinds of hardware platform structures of the software radio fuze are studied and the key techniques are analysed. The software radio fuze will become the most promising radio fuze techniques in 21st century.

Domain-Oriented Software Defined Computing Architecture

With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggregation of domain applications,domain-oriented computing architecture has become the technical direction that considers the high flexibility and efficiency of information system.Aiming at the characteristics of data-intensive computing in different scenarios such as Internet of Things(IoT),big data,artificial intelligence(AI),this paper presents a domain-oriented software defined computing architecture,discusses the hierarchical interconnection structure,hybrid granularity computing element and its computational kernel extraction method,finally proves the flexibility and high efficiency of this architecture by experimental comparison.

A Glance at the Middleware Technology

After describing the concept of middleware,this paper discusses the position and value of middleware among modern software technologies,summarizes some kinds of common middleware.This paper also gives some proposals for developing middleware in China.

The Software Industry Promotes All-round Cooperation

Software can be seen almost everywhere and is now defining the world.Software has transitioned from an affiliate of hardware,to a network service that is present in every corner of our social lives.

System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec

Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.

从ware到software

随着电子计算机的日益普及,今天在美国由—ware这个构词成分所组成的词屡屡可见。据美国哈佛大学的教育学教授 Howard Gardner声称,在近期召开的一次有关人工智能的学术会议之后,—ware词突然变得风靡起来。一位长期从事人类记忆研究的神经生物家甚至说,他觉得自已还不能适应这种情况,完全成了“a student of wetware among thecomputer hackers”(处在电子计算机专家中间一名学生)。从80年代初开始,wetware一词便被用来指 human brain。本来也可以用另外几个词:skullware,grayware(gray

Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective

Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional workloads.Therefore,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph algorithm.While domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software codesigns.This article presents a graph processing ecosystem from hardware to software.We start by introducing a series of hardware accelerators as the foundation of this ecosystem.Subsequently,the codesigned parallel graph systems and their distributed techniques are presented to support graph applications.Finally,we introduce our efforts on novel graph applications and hardware architectures.Extensive results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

复杂三维体高效布尔运算技术的研究与实现

高效、稳健的复杂三维体布尔运算是地理信息中的重点与难点。针对难点提出软硬件协同加速计算框架。在软件层面采用多种算法加速优化技术,包括:降维碰撞检测、三维多边形保留与丢弃的原则、新生成三维多边形的构建方法、三维线段与三维多边形的高效求交、三维点或三维多边形与三维体包含关系的高效判断;基于以上加速优化技术提出一套高效的计算框架;在硬件层面基于GPU的众核算力加速计算,提出软硬件协同加速计算框架。实验证明,该计算框架高效性且稳健性,与现有的方法相比,软件层面计算框架效率提高3倍左右,软硬件协同加速框架将效率进一步提高3倍左右。

草方格沙障铺设车控制系统设计

为提高草方格沙障铺设车自动化水平,降低人工劳动强度,提高工作效率,设计电子控制方法对机械机构进行控制。首先介绍铺设车作业流程,以西门子1200系列PLC作为控制核心设计控制方法,其次根据工作环境特点完成硬件选择和整体架构,并绘制控制系统接线原理图,然后根据工作需求对控制程序进行编写与仿真调试,最后对HMI进行组态。通过控制程序在Protal软件中的仿真运行,验证其能满足预期控制功能要求。

石化行业LDAR智能监管系统软硬件测试模型研究

LDAR系统集成了LDAR智能监管平台软件、LDAR移动端APP以及VOC工业气体检测仪器等硬件组件,实现了对工业危险气体泄漏的实时监测与管理。文章重点探讨了软硬件结合测试在确保该系统整体性能、稳定性和可靠性方面的关键作用。采用黑盒测试、白盒测试与灰盒测试相结合的方法,全面覆盖了软件的各个模块及功能点,确保了软件的质量与稳定性。同时,文章对硬件进行了持续的监控与分析,旨在及时识别并解决可能存在的潜在问题。实验结果表明,这种综合测试方法显著提升了LDAR系统的运行效率与检测准确性,对于减少工业气体污染、提升环保管理水平具有重要意义。

阀门电气控制柜自动测试方法研究

随着工业自动化水平的不断提高,自动测试技术已经得到广泛运用。阀门电气控制柜作为核电控制系统中的重要组成部分,传统的测试方法依赖于人工操作,测试效率和准确性较低。该文首先分析阀门电气控制柜测试原理及传统测试方法的局限性,随后详细阐述基于LabVIEW的自动测试系统的设计原理、总体架构,软硬件组成和关键的测试流程。通过实际测试验证该系统在提高测试效率方面的显著优势。该自动测试方法为阀门电气控制柜提供一套高效、可靠的测试手段,同时也为其他类似设备的自动测试提供参考和借鉴。

基于人工智能的博物馆智慧照明自动化控制系统研究

照明设计是博物馆建设中重要的一环,影响着参观者的观展体验,对博物馆照明系统展开智能化自动控制是目前博物馆研究的重点问题之一。传统的博物馆照明系统多通过人工控制方式完成,易造成资源的浪费,为了解决传统方法中存在的问题,提出基于人工智能的博物馆智慧照明自动化控制系统研究。该文建立了基于人工智能技术的博物馆智慧照明自动化控制系统架构并完成各部分的硬件设计,包含博物馆智慧照明终端控制模块、灯光控制模块、通信传输模块、传感采集控制模块和远程控制模块的五大系统功能模块,并利用智慧照明控制算法实现博物馆智慧照明控制。实验结果表明,所提方法的博物馆智慧照明自动化控制系统智能化程度高、耗能少、整体应用效果更佳。

基于STM32的配电网单相接地故障定位系统的设计

配电网故障定位系统对电网供电可靠性具有重要意义。针对配电网单相接地故障,利用某高压实验平台搭建10 kV配电网仿真模型,提取零序电流暂态分量作为故障特征量,以STM32为主控芯片,设计了一套符合中小型企业的配电网故障定位系统。该定位系统硬件设计方面主要包括数据采集模块、数据处理模块、运算控制单元和通信模块;软件设计方面主要包括模数转换程序、故障定位程序。测试表明,该定位系统能够准确、及时地判断出配电网单相接地故障发生的区间段。

基于自主可控软硬件的多节点异构运维管理方法及系统

多节点异构环境在信息技术高速发展的今天,已经成为企业IT基础架构中较为普遍的一种。本文旨在设计和实现一个基于自主可控软硬件的多节点异构运维管理系统,提高运维效率、降低成本、增强安全性和可靠性。研究内容涉及系统架构设计、管理策略与算法、资源调度与优化、安全与可靠性保障等多个方面。通过实际的调配与测试,展现了不俗的表现与用户的满意度。本研究不仅为多节点异构运维管理提供了有效的解决方案,同时也为今后的运维管理研究提供了一种新的思路和方法。