Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

An efficient GPU-based parallel tabu search algorithm for hardware/software co-design

Hardware/software partitioning is an essential step in hardware/software co-design.For large size problems,it is difficult to consider both solution quality and time.This paper presents an efficient GPU-based parallel tabu search algorithm(GPTS)for HW/SW partitioning.A single GPU kernel of compacting neighborhood is proposed to reduce the amount of GPU global memory accesses theoretically.A kernel fusion strategy is further proposed to reduce the amount of GPU global memory accesses of GPTS.To further minimize the transfer overhead of GPTS between CPU and GPU,an optimized transfer strategy for GPU-based tabu evaluation is proposed,which considers that all the candidates do not satisfy the given constraint.Experiments show that GPTS outperforms state-of-the-art work of tabu search and is competitive with other methods for HW/SW partitioning.The proposed parallelization is significant when considering the ordinary GPU platform.

SoftSSD:enabling rapid flash firmware prototyping for solid-state drives

Recently,solid-state drives(SSDs)have been used in a wide range of emerging data processing systems.Essentially,an SSD is a complex embedded system that involves both hardware and software design.For the latter,firmware modules such as the flash translation layer(FTL)orchestrate internal operations and flash management,and are crucial to the overall input/output performance of an SSD.Despite the rapid development of new SSD features in the market,the research of flash firmware has been mostly based on simulations due to the lack of a realistic and extensible SSD development platform.In this paper,we propose SoftSSD,a software-oriented SSD development platform for rapid flash firmware prototyping.The core of SoftSSD is a novel framework with an event-driven programming model.With the programming model,new FTL algorithms can be implemented and integrated into a full-featured flash firmware in a straightforward way.The resulting flash firmware can be deployed and evaluated on a hardware development board,which can be connected to a host system via peripheral component interconnect express and serve as a normal non-volatile memory express SSD.Different from existing hardware-oriented development platforms,SoftSSD implements the majority of SSD components(e.g.,host interface controller)in software,so that data flows and internal states that were once confined in the hardware can now be examined with a software debugger,providing the observability and extensibility that are critical to the rapid prototyping and research of flash firmware.We describe the programming model and hardware design of SoftSSD.We also perform experiments with real application workloads on a prototype board to demonstrate the performance and usefulness of SoftSSD,and release the open-source code of SoftSSD for public access.

Key technologies of system on chip design

The most supreme characteristic of SoC （system on chip） era is the high complexity of the chips; architecture and software design have become the indivisible part of chip design. As semiconductor fabrication technology evolves into very deep sub-micron （DSM） level, power consumption has become the inevitable challenge in SoC design. In order to maximize the lifetime of portable system battery, SoC is required not only to be energy-efficient but also to work in an optimal and battery-aware manner. This paper intends to discuss some key technologies of SoC design from the above perspectives of view.

Power optimization and performance improvement for embedded Ethernet SOC

Information appliance is the combination of traditional home appliances and the internet technology. In this article, an Ethernet controller system-on-chip （SOC） solution for information appliances is presented. To achieve high performance, the embedded 8 bits 8051 micro control unit （MCU） is optimized by an independent instruction bus and a data bus. Besides, a two-stage pipeline feature is added. Compared with the existing 8051 core, the enhanced one-cycle MCU offers ten times improvement in instruction execution efficiency. Meanwhile, the performance of media access control （MAC） circuit is greatly improved by adopting various techniques such as direct memory access （DMA） control, paging strategy, etc. To reduce the power consumption, clock gating, low power supply, and multi-working-clock are adopted. Moreover, to achieve rapid data communication in different clock frequency circuits, a simple ping-pong first in first out （FIFO） circuit is realized. The chip is implemented using TSMC 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology. Its die area is 4.8 min× 4.6 mm. The test results show that the maximum throughput of Ethernet packets can reach 7 Mb/s while the power consumption is rather low-the working current is just about 200 mA.