Strategy and Methodology of Integration Testing for GUI Software

In this paper, by means of effective testing practices, main strategies of integration testing for GUI software, including differentiating strategy for distinguished system, strategy of personnel organization, incremental testing strategy based on baseline version, testing strategy of circulating loop through the whole life, and the strategy of test suite construction, were briefly investigated. Moreover, for the code analysis, the FTA (Fault Tree analysis) is proposed to deal with the software change in regression testing. For test suite constructing, the constructing methods for baseline version and the incremental change are deeply discussed, in which main points focus on the testing strategy based on “Sheet/Form”, the “Grey-box approach” for integration testing process, and the application of the improved STD (State Transform Diagram) in state testing. At the same time, the suite construction of integration testing for two types, including small scale program and large scale software, is analyzed and discussed in detail. For testing execution, the specific method based on “Cross-testing” is investigated. Concurrently, by a lot of examples, all results of testing activity indicate that these strategies and methods are useful and fitted to integration testing for GUI software.

Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System

In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Script-Based GPU-Ready ELM Development for Continuous Code Integration

Designing and optimizing complex scientific code for new computing architectures is a challenging task. To address this issue in the E3SM land model (ELM) development, we developed a software tool called SPEL, which facilitates code generation, verification, and performance tuning using compiler directives within a Function Unit Test framework. In this paper, we present a SPEL extension that leverages the version control system (e.g., Git) to autonomous code generation and demonstrate its application to continuous code integration and development of the ELM software system. The study can benefit the scientific software development community.

Secrecy Outage Probability for Two-Way Integrated Satellite Unmanned Aerial Vehicle Relay Networks with Hardware Impairments

In this paper,we investigate the secrecy outage performance for the two-way integrated satellite unmanned aerial vehicle relay networks with hardware impairments.Particularly,the closed-form expression for the secrecy outage probability is obtained.Moreover,to get more information on the secrecy outage probability in a high signalto-noise regime,the asymptotic analysis along with the secrecy diversity order and secrecy coding gain for the secrecy outage probability are also further obtained,which presents a fast method to evaluate the impact of system parameters and hardware impairments on the considered network.Finally,Monte Carlo simulation results are provided to show the efficiency of the theoretical analysis.

Integrating Project Management, Software Development, and Knowledge Management Models: A Case Study in a Public ICT Services Organization

In project-based organizations knowledge is a critical resource used to develop and deliver products and services with a high level of quality. Therefore, a systematic and sustainable process is necessary to coordinate knowledge management, project management and product lifecycle. This scenario predominates in companies focused on the creation and maintenance of information systems. This article presents an exploratory study based on a framework that integrates cognitive, managerial, and operational processes in a public Brazilian organization that provides services in the area of information and communications technology, focusing on the construction and maintenance of information systems. Those processes are operationalized by three management models considering knowledge, project, and software development processes. Our proposal aims to understand the relationships between those three management models and their influence on the software development process in the organization under study. Our premise is based on the principle that cognitive management, project management, and software development management must be integrated to fulfill the demands of product development and service provision. The research data was composed of registers of working hours spent on software development and maintenance projects involving 244 people allocated to 5064 projects in the period from 2007 to 2013. The study resulted in the identification of the relationships among the three management models adopted by the organization, with emphasis on knowledge management activities, which were not directly identified, making it difficult to account for and measure them. We established a set of activities connected to each one of the knowledge management model phases. Since those activities were not visible before, our approach contributed to build a systematic process to register and relate activities linked to the dimensions of cognitive processes, project management, and software construction.

Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

A hardware/software co-optimization approach for embedded software of MP3 decoder

In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.

Application of Capability Maturity Model Integration to Innovation Management for Software and Service Companies

To look through innovation management in small project-based firms, such as software engineering companies, which are service firms that conduct projects for their clients, capability maturity model integration （CMMI） is introduced. It is a process improvement approach that provides organizations with the essential elements of effective processes. Taking ABC Software Company as an example, the performances before and after the introduction of CMMI in the firm were compared. The results indicated that after two years of application, the productivity increased 92%, and the ability of detecting errors improved 26.45% ; while the rate of faults and the cost of software development dropped 12.45% and 77.55%, respectively. To conclude, small project-based firms benefit a lot if they take CMMI into their process of innovation management, particularly for those R＆D firms, since the implementation of CMMI leads them to a promising future with higher efficiency and better effects.

A Novel Pipelining Encryption Hardware System with High Throughput and High Integration for 5G

This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

Research on The Software Development Ability Training With Gradual and Whole Process Based on The Deep Integration Between Industry and Education

In view of the mechanism and quality problems in the software ability training of computer majors in colleges and universities,as well as the engineering ability and innovation ability training results can not effectively meet the needs of society,this paper discusses how to realize the deep integration of production and education through school enterprise cooperation under the existing training mode.Through the establishment of a progressive whole process training system,students’software ability can be improved in an all-round way.Taking Shenyang Aerospace University as an example,it expounds how to organically combine the theoretical teaching in class with the cultivation of extracurricular innovation ability,and gradually guide students to comprehensively improve their software development ability and innovation ability.The model has been running for many years,and plays a leading role in promoting the reform of education and teaching and improving the quality of education,and provides reference for the brotherly colleges and universities.

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction

We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.

Linkage analysis and integrated software GAPL for pure-line populations derived from four-way and eight-way crosses

Pure lines derived from multiple parents provide abundant variation for genetic study.However,efficient genetic analysis methods and user-friendly software are still lacking.In this study, we developed linkage analysis methods and integrated analysis software for pure-line populations derived from four-way and eight-way crosses.First, polymorphic markers are classified into different categories according to the number of identifiable alleles in the inbred parents.Expected genotypic probability is then derived for each pair of complete markers, and based on them a maximum likelihood estimate(MLE) of recombination frequency is calculated.An EM algorithm is proposed for calculating recombination frequencies in scenarios that at least one marker is incomplete.A linkage map can thus be constructed using estimated recombination frequencies.We describe a software package called GAPL for recombination frequency estimation and linkage map construction in multi-parental pure-line populations.Both simulation studies and results from a reported four-way cross recombinant inbred line population demonstrate that the proposed method and software can build more accurate linkage maps in shorter times than other published software packages.The GAPL software is freely available from www.isbreeding.net and can also be used for QTL mapping in multi-parental populations.

The Impact of Delay in Software-Defined Integrated Terrestrial-Satellite Networks

Satellite communication networks have been evolving from standalone networks with ad-hoc infrastructures to possibly interconnected portions of a wider Future Internet architecture. Experts belonging to the fifth-generation(5 G) standardization committees are considering satellites as a technology to integrate in the 5 G environment. Software Defined Networking(SDN) is one of the paradigms of the next generation of mobile and fixed communications. It can be employed to perform different control functionalities, such as routing, because it allows traffic flow identification based on different parameters and traffic flow management in a centralized way. A centralized set of controllers makes the decisions and sends the corresponding forwarding rules for each traffic flow to the involved intermediate nodes that practically forward data up to the destination. The time to perform this process in integrated terrestrial-satellite networks could be not negligible due to satellite link delays. The aim of this paper is to introduce an SDN-based terrestrial satellite network architecture and to estimate the mean time to deliver the data of a new traffic flow from the source to the destination including the time required to transfer SDN control actions. The practical effect is to identify the maximum performance than can be expected.

Software Metric Analysis of Open-Source Business Software

Over the past decade, open-source software use has grown. Today, many companies including Google, Microsoft, Meta, RedHat, MongoDB, and Apache are major participants of open-source contributions. With the increased use of open-source software or integration of open-source software into custom-developed software, the quality of this software component increases in importance. This study examined a sample of open-source applications from GitHub. Static software analytics were conducted, and each application was classified for its risk level. In the analyzed applications, it was found that 90% of the applications were classified as low risk or moderate low risk indicating a high level of quality for open-source applications.

Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective

Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional workloads.Therefore,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph algorithm.While domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software codesigns.This article presents a graph processing ecosystem from hardware to software.We start by introducing a series of hardware accelerators as the foundation of this ecosystem.Subsequently,the codesigned parallel graph systems and their distributed techniques are presented to support graph applications.Finally,we introduce our efforts on novel graph applications and hardware architectures.Extensive results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

Finite element based design of software for integrated passive and active vibration control

Presents the design scheme developed for design of software for Integrated Passive and Active Vibration Control(IPAVC) and the coding of a prototyne system, and the selection of the famous finite element program MSC/NASTRAN as an important module of software to deal with large and complicated structures and systems with an example to demonstrate the prototype system.