Schottky barrier MOSFET structure with silicide source/drain on buried metal

In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal （SSDOM）. The source/drain region consists of two layers of silicide materials. Two Schottky barriers are formed between the silicide layers and the silicon channel. In the device design, the top barrier is lower and the bottom is higher. The lower top contact barrier is to provide higher on-state current, and the higher bottom contact barrier to reduce the off-state current. To achieve this, ErSi is proposed for the top silicide and CoSi2 for the bottom in the n-channel ease. The 50 nm n-channel SSDOM is thus simulated to analyse the performance of the SSDOM device. In the simulations, the top contact barrier is 0.2e V （for ErSi） and the bottom barrier is 0.6 eV （for CoSi2）. Compared with the corresponding conventional Schottky barrier MOSFET structures （CSB）, the high on-state current of the SSDOM is maintained, and the off-state current is efficiently reduced. Thus, the high drive ability （1.2 mA/μm at Vds = 1 V, Vgs = 2 V） and the high Ion/Imin ratio （10^6） are both achieved by applying the SSDOM structure.

Elevated Source/Drain Engineering by Novel Technology for Fully-Depleted SOI CMOS Devices and Circuits

m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per-stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.

Effects of source-drain underlaps on the performance of silicon nanowire on insulator transistors

The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.

Ge Complementary Tunneling Field-Effect Transistors Featuring Dopant Segregated NiGe Source/Drain

Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope（S factor）. Especially, I_d of 0.2 μA/μm is revealed at V_g-V_（th） = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.

FinFET Performance Enhancement by Source/Drain Cavity Structure Optimization

Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance.In this study,for the first time,we demonstrate methods of enhancing p-channel FinFET(pFET)performance on a fully integrated advanced FinFET platform via source/drain(S/D)cavity structure optimization.By modulating the cavity depth and proximity around the optimal reference point,we show that the trade-off between the S/D resistance and short channel effect,as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization.An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.

The modulation of Schottky barrier height of NiSi/n-Si Schottky diodes by silicide as diffusion source technique

This paper reports that the Schottky barrier height modulation of NiSi/n-Si is experimentally investigated by adopting a novel silicide-as-diffusion-source technique, which avoids the damage to the NiSi/Si interface induced from the conventional dopant segregation method. In addition, the impact of post-BF2 implantation after silicidation on the surface morphology of Ni silicides is also illustrated. The thermal stability of Ni silicides can be improved by silicide- as-diffusion-source technique. Besides, the electron Schottky barrier height is successfully modulated by 0.11 eV at a boron dose of 1015 cm-2 in comparison with the non-implanted samples. The change of barrier height is not attributed to the phase change of silicide films but due to the boron pile-up at the interface of NiSi and Si substrate which causes the upward bending of conducting band. The results demonstrate the feasibility of novel silicide-as-diffusion-source technique for the fabrication of Schottky source/drain Si MOS devices.

Improved power simulation of AlGaN/GaN HEMT at class-AB operation via an RF drain–source current correction method

A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（Al Ga N/Ga N-based HEMT） at high power operation. Since an accurate radio frequency（RF） current simulation is critical for a correct power simulation of the device, in this paper we propose a method of Al Ga N/Ga N high electron mobility transistor（HEMT）nonlinear large-signal model extraction with a supplemental modeling of RF drain–source current as a function of RF input power. The improved results of simulated output power, gain, and power added efficiency（PAE） at class-AB quiescent bias of Vgs =-3.5 V, Vds= 30 V with a frequency of 9.6 GHz are presented.

Observation of source/drain bias-controlled quantum transport spectrum in junctionless silicon nanowire transistor

We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.

Photoluminescence from neodymium silicide thin films formed by MEVVA ion source

Neodymium silicides were synthesized by Nd ion implant6d into Si substrates with the aid of a metal vapor vacuum arc (MEVVA) ion source. The blender of Nd5Si4 and NdSi2 was formed in a neodymium-implanted silicon thin film during the as-implanted state, but there was only single neodymium silicide compound in the postannealed state, and the phase changed from NdSi2 to Nd5Si4 with increasing annealing temperature. The blue-violet luminescence excited by ultra-violet was observed at the room temperature (RT), and the intensity of photoluminescence (PL) increased with increasing the neodymium ion fluence. Moreover, the photoluminescence was closely dependent on the temperature of rapid thermal annealing (RTA). A mechanism of photoluminescence was discussed.

A threshold voltage model of short-channel fully-depleted recessed-source/drain(Re-S/D) SOI MOSFETs with high-k dielectric

In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.

Numerical Analysis of Gate-to-Source Distance Effects in SiC MESFETs

Two-dimensional DC and small-signal analysis of gate-to-source scaling effects in SiC-based high-power field-effect transistors have been performed in this paper. The simulation results show that a downscaling of gate-to-source distance can improve device performance, i.e. enhancing drain current, transconductance, and maximum oscillation frequency. This is associated with the peculiar dynamic of electrons in SiC MESFETs, which lead to a linear velocity regime in the source access region. The variations of gate-to-source capacitance, gate-to-drain capacitance, and cut-off frequency with respect to the change in gate-to-source length have also been studied in detail.

适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究

SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。

高压大功率SiC MOSFETs短路保护方法

碳化硅(SiC)MOSFETs短路承受能力弱,研究其短路保护方法成为保障电力电子设备安全运行的重要课题。现有方法大多围绕低压小功率SiC MOSFETs,然而随着电压和功率等级的提升,器件特性有所差异,直接套用以往设计难以实现高压大功率SiC MOSFETs的快速、可靠保护。该文首先详细研究了几种常用短路检测方法;其次基于高压大功率SiC MOSFETs器件特性,深入对比分析了不同短路检测方法的适用性,提出一种阻容式漏源极电压检测和栅极电荷检测相结合的短路保护方法;最后搭建了实验平台验证所提方法的可行性。结果表明,提出的方法在硬开关短路故障(hard switching fault,HSF)下,保护响应时间缩短了1.4μs,短路能量降低了62.5%;且能可靠识别负载短路故障(fault under load,FUL)。

GaN HEMT源漏通道区电阻的自热和准饱和效应模型

GaN HEMT在栅极与源极和漏极之间存在一段通道区域,在等效电路模型中通常等效为一电阻,称为源漏通道区电阻R_(D,S)。准确构建GaN HEMT R_(D,S)模型,对于分析GaN HEMT直流和射频特性,构建GaN HEMT大信号模型具有十分重要的意义。本研究给出考虑自热和准饱和效应的R_(D,S)模型。首先由源漏通道区温度T_(CH)与耗散功率P_(diss)的关系,推导出非线性自热效应模型。进一步基于准饱和效应和Trofimenkoff模型,给出源漏通道区电子漂移速度与电场强度的关系表达式,构建非线性R_(D,S)模型。在环境温度Tamb=300~500 K时,源漏通道区二维电子气2DEG面密度n_(S,acc)(T_(CH))和迁移率μ_(acc)(T_(CH))随T_(CH)的升高而下降,这导致低偏置条件下的源漏通道区电阻R_(D0,S0)随T_(CH)呈非线性增长。将本研究和文献报道的R_(D,S)模型与TCAD(Technology Computer Aided Design)仿真数据进行对比,结果显示:本研究与文献报道的漏通道区电阻RD模型的平均相对误差分别为0.32%和1.78%,均方根误差(RMSE)分别为0.039和0.20Ω;RS模型的平均相对误差分别为0.76%和1.73%,RMSE分别为0.023和0.047Ω。与文献报道的实验数据进行对比,结果显示:本研究与文献RD模型的平均相对误差分别为0.91%和1.59%,RMSE分别为0.012和0.015Ω;RS平均相对误差分别为1.22%和2.77%,RMSE分别为0.0015和0.0034Ω。本研究提出的R_(D,S)模型具有更低的平均相对误差和均方根误差,能够更加准确地表征GaN HEMT线性工作区R_(D,S)随漏源电流I_(DS)的变化。可将本模型用于器件的设计优化,也可作为Spice模型用于电路仿真。

珠江源曲靖南盘江污染特征分析及对策措施

南盘江是珠江源头、云南曲靖人民的母亲河,其综合系统治理关系到曲靖的生态环境改善和经济社会的可持续发展。为精准掌握南盘江流域水污染问题,本研究详细分析了水质时空变化,降雨时城区管网溢流情况,沿岸排污口分布及污染物排放、合流制截污管网覆盖及漏损情况,南盘江干流闸坝运行调度情况。结果表明:南盘江流域水质劣Ⅴ类,重度污染,水质旱季劣于雨季,支流劣于干流,下游劣于上游,主要超标因子为NH 3-N和TP;当城区降雨量高于约10 mm时,部分支流白石江等雨水口大量生活污水溢流,雨污合流制难以应对降雨天气;干支流共有排口225个,抽检50个排口水质达标率约24%,超标排放情况普遍;曲靖城区城市建设落后,建成区约30 km 2采用雨污合流制,仍有约40%区域未覆盖截污管网;城区人均水资源量760 m 3,仅为云南人均的15.6%,全国的36%,沿岸闸坝蓄水满足农业灌溉用水需求,闸坝运行调度混乱,河道生态流量无法保障。建议以河长制为抓手,加强工业及城镇生活点源污染治理,优化区域水资源配置,推进河道综合治理、理顺管理机制体制,构建快处高效的治理执行体系,形成全社会参与的南盘江治理局面,方能促进南盘江水生态环境质量持续改善,惠及民生,还河于民。

Evaluation of the drain–source voltage effect on AlGaAs/InGaAs PHEMTs thermal resistance by the structure function method

The effect of drain-source voltage on A1GaAs/InGaAs PHEMTs thermal resistance is studied by experimental measuring and simulation. The result shows that A1GaAs/InGaAs PHEMTs thermal resistance presents a downward trend under the same power dissipation when the drain-source voltage （VDs） is decreased. Moreover, the relatively low VDS and large drain-source current （IDs） result in a lower thermal resistance. The chip-level and package-level thermal resistance have been extracted by the structure function method. The simulation result indicated that the high electric field occurs at the gate contact where the temperature rise occurs. A relatively low VDS leads to a relatively low electric field, which leads to the decline of the thermal resistance.

An improved performance of copper phthalocyanine OFETs with channel and source/drain contact modifications

We report an effective method to improve the performance of p-type copper phthalocyanine （CuPc） based organic field-effect transistors （OFETs） by employing a thin para-quaterphenyl （p-4p） film and simultane- ously applying V205 to the source/drain regions. The p-4p layer was inserted between the insulating layer and the active layer, and V205 layer was added between CuPc and A1 in the source-drain （S/D） area. As a result, the field- effect saturation mobility and on/off current ratio of the optimized device were improved to 5 × 10-2 cm2/（V.s） and 104, respectively. We believe that because p-4p could induce CuPc to form a highly oriented and continuous film, this resulted in the better injection and transport of the carriers. Moreover, by introducing the V205 electrode＇s modified layers, the height of the carrier injection barrier could be effectively tuned and the contact resistance could be reduced.

High performance AlGaN/GaN HEMTs with 2.4μm source-drain spacing

This paper describes the performance of AIGaN/GaN HEMTs with 2.4μm source-drain spacing. So far these are the smallest source-drain spacing AIGaN/GaN HEMTs which have been implemented with a domestic wafer and domestic process. This paper also compares their performance with that of 4μm source-drain spacing devices. The former exhibit higher drain current, higher gain, and higher efficiency. It is especially significant that the maximum frequency of oscillation noticeably increased.

Influence of gate-source/drain misalignment on the performance of bulk FinFETs by a 3D full band Monte Carlo simulation

We investigate the influence of gate-source/drain （G-S/D） misalignment on the performance of bulk fin field effect transistors （FinFETs） through the three-dimensional （3D） full band Monte Carlo simulator. Several scat- tering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.

离子注入形成FeSi_2埋层的电镜研究

利用ＭＥＶＶＡ离子源将Ｆｅ离子注入到Ｓｉ基体中会生成一层铁硅化物薄膜．利用电子显微镜，研究了这层铁硅化物的显微结构及其在随后的升温退火过程中发生的变化．研究结果表明，在离子注入剂量为１×１０１７／ｃｍ２的未退火样品中，亚稳的γ－ＦｅＳｉ２相占大多数，同时有少量的由ＣｓＣｌ结构派生的缺陷相Ｆｅ１－ＸＳｉ．在（１００）取向的Ｓｉ片上，这个硅化物层埋在硅基体中。