A novel simple two-dimensional square-lattice model of amphiphile at oil-water interface is developed,in which oil and water act as solvent and occupy empty sites and amphiphile occupies chains of sites. In this mode...A novel simple two-dimensional square-lattice model of amphiphile at oil-water interface is developed,in which oil and water act as solvent and occupy empty sites and amphiphile occupies chains of sites. In this model, the oil-water interface is fixed, And amphiphile molecules will be enriched at the oil-water interface. The interfacial concentration of amphiphile calculated by Monte Carlo method shows that it is easier for the hydrophilic-hydrophobic balanced amphiphile to stay at the interface. And the adsorption of amphiphile increases with the increase of amphiphile concentration and the decrease with temperature.展开更多
Amphiphile-oil-water system is complicated. The real behavior of amphiphile in the interface is still undnown despite that this behavior is very important in determining the stability of emulsion system. In this paper...Amphiphile-oil-water system is complicated. The real behavior of amphiphile in the interface is still undnown despite that this behavior is very important in determining the stability of emulsion system. In this paper, the interface properties of amphiphile at oil-water interface were investigated by a square-lattice model Monte Carlo simulation method. The synergistic effect was found for hydrophobic and hydrophilic amphiphile mixture systems; and the synergistic effect disappears or was weakened as the amphiphile at the interface region became dilute with the increasing of temperature.展开更多
The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is me...The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.展开更多
The forward gated-diode R-G current method is used to monitor the F-N stressing-induced interface traps of NMOSFET/SOI.This simp le and accurate experiment method can directly give the interface trap density i nduced...The forward gated-diode R-G current method is used to monitor the F-N stressing-induced interface traps of NMOSFET/SOI.This simp le and accurate experiment method can directly give the interface trap density i nduced by F-N stressing effect for characterizing the device's reliability.For the measured NMOS/SOI device with a body structure,an expected power-law relati onship as Δ N it - t 0 4 between the pure F-N stressing-indu ced interface trap density and the accumulated stressing time is obtained.展开更多
Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give ...Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device’s hot carrier characteristics. For the tested device, an expected power law relationship of △Nit-t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.展开更多
A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of t...A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.展开更多
The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method dir...The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.展开更多
Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the princi...Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.展开更多
A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown character...A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.展开更多
Based on the circuit principle of 1186 Electro Chemical Interface preduced by Solartron Electronic Group Ltd., a precise electro chemical interface (ECI) unit, which can provide the interfacing requirements for the co...Based on the circuit principle of 1186 Electro Chemical Interface preduced by Solartron Electronic Group Ltd., a precise electro chemical interface (ECI) unit, which can provide the interfacing requirements for the control and measurement of characteristics of electro chemical cell, was developed by means of some essential improvements. Not only can it be used to control and measure the steady and non-steady state characteristics, but also it can be directly connected with Solartron 1170 series or 1250 Frequency Response Analysers (FRA) to measure the AC impedance. Besides,the EC1 can also be connected with two- or three-electrode electro chemical cell systems to test convenlently and correctly their DC and AC characteristics, and used as a four-electrode potentlostat combined with four-electrode electro chernical cell system which contains two reference electrodes (RES) for researches on the electro chemical characteristics of oil-water interface, etc.展开更多
基于求解二维Po isson方程,分析了具有埋氧层界面电荷的SO I结构纵向击穿特性,提出了界面电荷耐压模型。该模型通过埋氧层界面电荷来调制硅层和埋氧层电场,获得极高击穿电压。进一步提出临界界面电荷面密度概念,给出其工程化应用的近似...基于求解二维Po isson方程,分析了具有埋氧层界面电荷的SO I结构纵向击穿特性,提出了界面电荷耐压模型。该模型通过埋氧层界面电荷来调制硅层和埋氧层电场,获得极高击穿电压。进一步提出临界界面电荷面密度概念,给出其工程化应用的近似公式。并对文献中的不同结构SO I器件的纵向耐压进行计算。解析结果和试验结果或M ED IC I仿真结果吻合良好。展开更多
通过数值模拟手段，用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R－G电流大小的影响规律。结果表明：无论在FD还是在PD SOI MOS器件中，界面陷阱密度是决定R－G电流峰值的主要因素，硅膜厚度和沟道掺杂浓度的影响却因器...通过数值模拟手段，用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R－G电流大小的影响规律。结果表明：无论在FD还是在PD SOI MOS器件中，界面陷阱密度是决定R－G电流峰值的主要因素，硅膜厚度和沟道掺杂浓度的影响却因器件的类型而导。为了精确地用R－G电流峰值确定界面陷阱的大小，器件参数的影响也必须包括在模型之中。展开更多
基金Supported by the National Natural Science Foundation of China (No. 29736170)and the Natural Science Foundation of Zhejiang Province(No. RC01051).
文摘A novel simple two-dimensional square-lattice model of amphiphile at oil-water interface is developed,in which oil and water act as solvent and occupy empty sites and amphiphile occupies chains of sites. In this model, the oil-water interface is fixed, And amphiphile molecules will be enriched at the oil-water interface. The interfacial concentration of amphiphile calculated by Monte Carlo method shows that it is easier for the hydrophilic-hydrophobic balanced amphiphile to stay at the interface. And the adsorption of amphiphile increases with the increase of amphiphile concentration and the decrease with temperature.
基金Supported by the National Natural Science Foundation of China (No. 29736170) the Natural Science Foundation of Zhejiang Province (No. RC01051).
文摘Amphiphile-oil-water system is complicated. The real behavior of amphiphile in the interface is still undnown despite that this behavior is very important in determining the stability of emulsion system. In this paper, the interface properties of amphiphile at oil-water interface were investigated by a square-lattice model Monte Carlo simulation method. The synergistic effect was found for hydrophobic and hydrophilic amphiphile mixture systems; and the synergistic effect disappears or was weakened as the amphiphile at the interface region became dilute with the increasing of temperature.
文摘The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.
文摘The forward gated-diode R-G current method is used to monitor the F-N stressing-induced interface traps of NMOSFET/SOI.This simp le and accurate experiment method can directly give the interface trap density i nduced by F-N stressing effect for characterizing the device's reliability.For the measured NMOS/SOI device with a body structure,an expected power-law relati onship as Δ N it - t 0 4 between the pure F-N stressing-indu ced interface trap density and the accumulated stressing time is obtained.
基金Sponsored by Motorola-Peking University Joint Project.Contract No.:MSPSDDLCHINA-0004
文摘Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device’s hot carrier characteristics. For the tested device, an expected power law relationship of △Nit-t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60436030 and 60806025)
文摘A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.
基金special funds of major state basic research projects (G20000365)
文摘The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.
基金Project Supported by Motorola CPT(Contract No.MSPSESTL-CTC9903)
文摘Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060)the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904)the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721)
文摘A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.
文摘Based on the circuit principle of 1186 Electro Chemical Interface preduced by Solartron Electronic Group Ltd., a precise electro chemical interface (ECI) unit, which can provide the interfacing requirements for the control and measurement of characteristics of electro chemical cell, was developed by means of some essential improvements. Not only can it be used to control and measure the steady and non-steady state characteristics, but also it can be directly connected with Solartron 1170 series or 1250 Frequency Response Analysers (FRA) to measure the AC impedance. Besides,the EC1 can also be connected with two- or three-electrode electro chemical cell systems to test convenlently and correctly their DC and AC characteristics, and used as a four-electrode potentlostat combined with four-electrode electro chernical cell system which contains two reference electrodes (RES) for researches on the electro chemical characteristics of oil-water interface, etc.
文摘基于求解二维Po isson方程,分析了具有埋氧层界面电荷的SO I结构纵向击穿特性,提出了界面电荷耐压模型。该模型通过埋氧层界面电荷来调制硅层和埋氧层电场,获得极高击穿电压。进一步提出临界界面电荷面密度概念,给出其工程化应用的近似公式。并对文献中的不同结构SO I器件的纵向耐压进行计算。解析结果和试验结果或M ED IC I仿真结果吻合良好。
文摘通过数值模拟手段，用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R－G电流大小的影响规律。结果表明：无论在FD还是在PD SOI MOS器件中，界面陷阱密度是决定R－G电流峰值的主要因素，硅膜厚度和沟道掺杂浓度的影响却因器件的类型而导。为了精确地用R－G电流峰值确定界面陷阱的大小，器件参数的影响也必须包括在模型之中。
