Nowadays,the novel oil water interface method has attracted a considerable attention owing to the advantages of mild reaction conditions,simple operation,low cost,and high efficiency.In this paper,uniform oil-soluble ...Nowadays,the novel oil water interface method has attracted a considerable attention owing to the advantages of mild reaction conditions,simple operation,low cost,and high efficiency.In this paper,uniform oil-soluble Fe_3O_4 nanoparticles(NPs) were synthesized by oil-water interface method from mixing iron tristearate of 0.067mol/L in cyclohexane with ferrous sulfate in water.The as-prepared products were characterized by X-ray diffraction(XRD),transmission electron microscopy(TEM),vibrating sample magnetometer(VSM),Fourier transform infrared spectroscopy(FT-IR) and thermogravimetric analyzer(TGA).TEM images and XRD profiles showed that the size of the oil-soluble products ranged in 1.7-6.9 nm.VSM indicated that the Fe_3O_4 NPs were superparamagetic.FT-IR and TGA proved that oleic acid was combined to the surface of Fe_3O_4 NPs closely.TEM images and XRD profiles revealed that the most suitable reaction concentration of NH_3·H_2O,oleic acid/water in volume,reaction temperature and reaction time were 4.5 mol/L,50:1 000,80℃ and 6 h,respectively.The formation mechanism of the nearly monodispersed Fe_3O_4 NPs was that the preformed Fe_3O_4 nuclei were capped by oleic acid as early as the nucleation occurred in oil-water interface and subsequently entered into oil phase to stop growing.展开更多
A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of t...A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.展开更多
Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give ...Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device's hot carrier characteristics. For the tested device, an expected power law relationship of ANit ～ t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.展开更多
Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the princi...Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.展开更多
A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown character...A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.展开更多
The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method dir...The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.展开更多
基于求解二维Po isson方程,分析了具有埋氧层界面电荷的SO I结构纵向击穿特性,提出了界面电荷耐压模型。该模型通过埋氧层界面电荷来调制硅层和埋氧层电场,获得极高击穿电压。进一步提出临界界面电荷面密度概念,给出其工程化应用的近似...基于求解二维Po isson方程,分析了具有埋氧层界面电荷的SO I结构纵向击穿特性,提出了界面电荷耐压模型。该模型通过埋氧层界面电荷来调制硅层和埋氧层电场,获得极高击穿电压。进一步提出临界界面电荷面密度概念,给出其工程化应用的近似公式。并对文献中的不同结构SO I器件的纵向耐压进行计算。解析结果和试验结果或M ED IC I仿真结果吻合良好。展开更多
通过数值模拟手段，用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R－G电流大小的影响规律。结果表明：无论在FD还是在PD SOI MOS器件中，界面陷阱密度是决定R－G电流峰值的主要因素，硅膜厚度和沟道掺杂浓度的影响却因器...通过数值模拟手段，用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R－G电流大小的影响规律。结果表明：无论在FD还是在PD SOI MOS器件中，界面陷阱密度是决定R－G电流峰值的主要因素，硅膜厚度和沟道掺杂浓度的影响却因器件的类型而导。为了精确地用R－G电流峰值确定界面陷阱的大小，器件参数的影响也必须包括在模型之中。展开更多
SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件...SOI NLIGBT中热载流子效应分别通过直流电压的应力测试、TCAD仿真和电荷泵测试三种方法进行了研究。其中,不同直流电压应力条件下测得的衬底电流Isub和导通电阻Ron用来评估因热载流子效应引起的器件退化程度。为了进行理论分析,对器件内部的电场强度和碰撞离化率也进行了仿真。测试得到的电荷泵电流直接验证了器件表面的损伤程度。最后讨论了SOI LIGBT在不同栅压条件下的退化机制。展开更多
基金Nanometer Special Project of Shanghai,China(No.1052nm06400)
文摘Nowadays,the novel oil water interface method has attracted a considerable attention owing to the advantages of mild reaction conditions,simple operation,low cost,and high efficiency.In this paper,uniform oil-soluble Fe_3O_4 nanoparticles(NPs) were synthesized by oil-water interface method from mixing iron tristearate of 0.067mol/L in cyclohexane with ferrous sulfate in water.The as-prepared products were characterized by X-ray diffraction(XRD),transmission electron microscopy(TEM),vibrating sample magnetometer(VSM),Fourier transform infrared spectroscopy(FT-IR) and thermogravimetric analyzer(TGA).TEM images and XRD profiles showed that the size of the oil-soluble products ranged in 1.7-6.9 nm.VSM indicated that the Fe_3O_4 NPs were superparamagetic.FT-IR and TGA proved that oleic acid was combined to the surface of Fe_3O_4 NPs closely.TEM images and XRD profiles revealed that the most suitable reaction concentration of NH_3·H_2O,oleic acid/water in volume,reaction temperature and reaction time were 4.5 mol/L,50:1 000,80℃ and 6 h,respectively.The formation mechanism of the nearly monodispersed Fe_3O_4 NPs was that the preformed Fe_3O_4 nuclei were capped by oleic acid as early as the nucleation occurred in oil-water interface and subsequently entered into oil phase to stop growing.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60436030 and 60806025)
文摘A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.
基金Sponsored by Motorola-Peking University Joint Project.Contract No.:MSPSDDLCHINA-0004
文摘Forward gated-diode Recombination-Generation(R-G) current method is applied to an NMOSFET/SOI to measure the stress-induced interface traps in this letter. This easy but accurate experimental method can directly give stress-induced average interface traps for characterizing the device's hot carrier characteristics. For the tested device, an expected power law relationship of ANit ～ t0.787 between pure stress-induced interface traps and accumulated stressing time is obtained.
基金Project Supported by Motorola CPT(Contract No.MSPSESTL-CTC9903)
文摘Characterized back interface traps of SOI devices by the Recombination\|Generation (R\|G) current has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSIS\|ISE.The basis of the principle for the R\|G current’s characterizing the back interface traps of SOI lateral p\++p\+-n\++ diode has been demonstrated.The dependence of R\|G current on interface trap characteristics has been examined,such as the state density,surface recombination velocity and the trap energy level.The R\|G current proves to be an effective tool for monitoring the back interface of SOI devices.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060)the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904)the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721)
文摘A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.
基金special funds of major state basic research projects (G20000365)
文摘The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.
文摘基于求解二维Po isson方程,分析了具有埋氧层界面电荷的SO I结构纵向击穿特性,提出了界面电荷耐压模型。该模型通过埋氧层界面电荷来调制硅层和埋氧层电场,获得极高击穿电压。进一步提出临界界面电荷面密度概念,给出其工程化应用的近似公式。并对文献中的不同结构SO I器件的纵向耐压进行计算。解析结果和试验结果或M ED IC I仿真结果吻合良好。
文摘通过数值模拟手段，用归一化的方法研究了界面陷阱、硅膜厚度和沟道掺杂浓度对R－G电流大小的影响规律。结果表明：无论在FD还是在PD SOI MOS器件中，界面陷阱密度是决定R－G电流峰值的主要因素，硅膜厚度和沟道掺杂浓度的影响却因器件的类型而导。为了精确地用R－G电流峰值确定界面陷阱的大小，器件参数的影响也必须包括在模型之中。
