Sparse-tree land is one of the typical lands and can be considered as one typical rough surface in boundary layer meteorology. Many lands can be classified into the kind surface in the view of scaIe and distribution f...Sparse-tree land is one of the typical lands and can be considered as one typical rough surface in boundary layer meteorology. Many lands can be classified into the kind surface in the view of scaIe and distribution feature of the roughness elements such as agroforest, scatter planted or growing trees, savanna and so on. The structure of surface boundary layer in sparse-tree land is analyzed and the perameters, friction velocity u*and roughness length zo are deduced based on energy balance law and other physical hypothesis. The models agree well with data of wind tunnel experiments and field measurements.展开更多
This paper presents an optimized 64-bit parallel adder, Sparse-tree architecture enames low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simula...This paper presents an optimized 64-bit parallel adder, Sparse-tree architecture enames low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power.展开更多
文摘Sparse-tree land is one of the typical lands and can be considered as one typical rough surface in boundary layer meteorology. Many lands can be classified into the kind surface in the view of scaIe and distribution feature of the roughness elements such as agroforest, scatter planted or growing trees, savanna and so on. The structure of surface boundary layer in sparse-tree land is analyzed and the perameters, friction velocity u*and roughness length zo are deduced based on energy balance law and other physical hypothesis. The models agree well with data of wind tunnel experiments and field measurements.
基金Supported by the National Natural Science Foundation of China under Grant Nos. 60273069, 60376018, 90207011, the National High Technology Development 863 Program of China under Grant No. 2002AAl10020, and the Adwnced Research Foundation of NUDT under Grant No. JC03-06-007.
文摘This paper presents an optimized 64-bit parallel adder, Sparse-tree architecture enames low carry-merge fan-outs and inter-stage wiring complexity. Single-rail and semi-dynamic circuit improves operation speed. Simulation results show that the proposed adder can operate at 485ps with power of 25.6mW in 0.18μm CMOS process. It achieves the goal of higher speed and lower power.
