A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor(MOSFET)with a split gate(SG)and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode(SGHJD-TMOS)is investigated in this ar...A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor(MOSFET)with a split gate(SG)and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode(SGHJD-TMOS)is investigated in this article.The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gateoxide electric field.The integrated p^(+)-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device.Numerical analysis results show that,compared with the conventional asymmetric cell trench MOSFET(CA-TMOS),the high-frequency figure of merit(HF-FOM,R_(on,sp)×Q_(gd,sp))is reduced by 92.5%,and the gate-oxide electric field is reduced by 75%.In addition,the forward conduction voltage drop(V_(F))and gate-drain charge(Q_(gd))are reduced from 2.90 V and 63.5μC/cm^(2) in the CA-TMOS to 1.80 V and 26.1μC/cm^(2) in the SGHJD-TMOS,respectively.Compared with the CA-TMOS,the turn-on loss(E_(on)) and turn-off loss(E_(off)) of the SGHJD-TMOS are reduced by 21.1%and 12.2%,respectively.展开更多
A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(C_(RSS)).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In add...A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(C_(RSS)).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In addition to the poor static performance,the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering(DIBL)caused by the high gate oxide electric field.As such,a 3.3 kV 4 H-SiC split gate MOSFET with a grounded central implant region(SG-CIMOSFET)is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance.The SG-CIMOSFET has a significantly low on-resistance(R_(ON))and maximum gate oxide field(E_(OX))due to the central implant region.A grounded central implant region significantly reduces the C_(RSS)and gate drain charge(Q_(GD))by partially screening the gate-to-drain capacitive coupling.Compared to a planar MOSFET,the SG MOSFET,central implant MOSFET(CIMOSFET),the SGCIMOSFET improve the R_(ON)×Q_(GD)by 83.7%,72.4%and 44.5%,respectively.The results show that the device features not only the smallest switching energy loss but also the fastest switching time.展开更多
A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling a...A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling area between the split gate and the drain electrode is reduced,thus the gate-to-drain charge(Q_(GD)),reverse transfer capacitance(C_(RSS)) and turn-off loss(E_(off)) are significantly decreased.Moreover,the MOS-channel diode is controlled by the dummy gate with ultra-thin gate oxide t_(ox),which can be turned on before the parasitic P-base/N-drift diode at the reverse conduction,then the majority carriers are injected to the N-drift to attenuate the minority injection.Therefore,the reverse recovery charge(Q_(RR)),time(T_(RR)) and peak current(I_(RRM)) are effectively reduced at the reverse freewheeling state.Additionally,the specific on-resistance(R_(on,sp)) and breakdown voltage(BV) are also studied to evaluate the static properties of the proposed SD-MOS.The simulation results show that the Q_(GD) of 6 nC/cm^(2),the C_(RSS) of 1.1 pF/cm^(2) at the V_(DS) of 150 V,the QRR of 1.2 μC/cm^(2) and the R_(on,sp) of 8.4 mΩ·cm^(2) are obtained,thus the figures of merit(FOM) including Q_(GD) ×R_(on,sp) of50 nC·mΩ,E_(off) × R_(on,sp) of 0.59 mJ·mΩ and the Q_(RR) × R_(on,sp) of 10.1 μC·mΩ are achieved for the proposed SD-MOS.展开更多
A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structur...A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.展开更多
A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS d...A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.展开更多
基金Major Science and Technology Projects of Hainan Province,China(Grant Nos.ZDKJ2021023 and ZDKJ2021042)Hainan Provincial Natural Science Foundation of China(Grant Nos.622QN285 and 521QN210)。
文摘A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor(MOSFET)with a split gate(SG)and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode(SGHJD-TMOS)is investigated in this article.The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gateoxide electric field.The integrated p^(+)-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device.Numerical analysis results show that,compared with the conventional asymmetric cell trench MOSFET(CA-TMOS),the high-frequency figure of merit(HF-FOM,R_(on,sp)×Q_(gd,sp))is reduced by 92.5%,and the gate-oxide electric field is reduced by 75%.In addition,the forward conduction voltage drop(V_(F))and gate-drain charge(Q_(gd))are reduced from 2.90 V and 63.5μC/cm^(2) in the CA-TMOS to 1.80 V and 26.1μC/cm^(2) in the SGHJD-TMOS,respectively.Compared with the CA-TMOS,the turn-on loss(E_(on)) and turn-off loss(E_(off)) of the SGHJD-TMOS are reduced by 21.1%and 12.2%,respectively.
基金supported by the MSIT(Ministry of Science and ICT),Korea,under the ITRC(Information Technology Research Center)support program(IITP-2020-2018-0-01421)supervised by the IITP(Institute for Information&communications Technology Promotion)then Samsung Electronics.
文摘A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(C_(RSS)).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In addition to the poor static performance,the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering(DIBL)caused by the high gate oxide electric field.As such,a 3.3 kV 4 H-SiC split gate MOSFET with a grounded central implant region(SG-CIMOSFET)is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance.The SG-CIMOSFET has a significantly low on-resistance(R_(ON))and maximum gate oxide field(E_(OX))due to the central implant region.A grounded central implant region significantly reduces the C_(RSS)and gate drain charge(Q_(GD))by partially screening the gate-to-drain capacitive coupling.Compared to a planar MOSFET,the SG MOSFET,central implant MOSFET(CIMOSFET),the SGCIMOSFET improve the R_(ON)×Q_(GD)by 83.7%,72.4%and 44.5%,respectively.The results show that the device features not only the smallest switching energy loss but also the fastest switching time.
基金Project supported by the National Natural Science Foundation of China (Grants No. 61604027 and 61704016)the Chongqing Natural Science Foundation, China (Grant No. cstc2020jcyj-msxmX0550)。
文摘A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling area between the split gate and the drain electrode is reduced,thus the gate-to-drain charge(Q_(GD)),reverse transfer capacitance(C_(RSS)) and turn-off loss(E_(off)) are significantly decreased.Moreover,the MOS-channel diode is controlled by the dummy gate with ultra-thin gate oxide t_(ox),which can be turned on before the parasitic P-base/N-drift diode at the reverse conduction,then the majority carriers are injected to the N-drift to attenuate the minority injection.Therefore,the reverse recovery charge(Q_(RR)),time(T_(RR)) and peak current(I_(RRM)) are effectively reduced at the reverse freewheeling state.Additionally,the specific on-resistance(R_(on,sp)) and breakdown voltage(BV) are also studied to evaluate the static properties of the proposed SD-MOS.The simulation results show that the Q_(GD) of 6 nC/cm^(2),the C_(RSS) of 1.1 pF/cm^(2) at the V_(DS) of 150 V,the QRR of 1.2 μC/cm^(2) and the R_(on,sp) of 8.4 mΩ·cm^(2) are obtained,thus the figures of merit(FOM) including Q_(GD) ×R_(on,sp) of50 nC·mΩ,E_(off) × R_(on,sp) of 0.59 mJ·mΩ and the Q_(RR) × R_(on,sp) of 10.1 μC·mΩ are achieved for the proposed SD-MOS.
基金Project supported by“Efficient and Energy-Saving GaN on Si Power Devices”Research Fund(Grant No.KQCX20140522151322946)the Research Fund of the Third Generation Semiconductor Key Laboratory of Shenzhen,China(Grant No.ZDSYS20140509142721434)+1 种基金the“Key Technology Research of GaN on Si Power Devices”Research Fund(Grant No.JSGG20140729145956266)the“Research of Low Cost Fabrication of GaN Power Devices and System Integration”Research Fund(Grant No.JCYJ201602261926390)
文摘A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.
基金Project supported by the National Natural Science Foundation of China (Grant No. 60906048)the Program for New Century Excellent Talents in University,China (Grant No. NCET-10-0052)the Fundamental Research Funds for the Central Universities,China (Grant No. HEUCFT1008)
文摘A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.
