Spurious signals in direct digital frequency synthesizers (DDFSs) are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These si...Spurious signals in direct digital frequency synthesizers (DDFSs) are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These signals are deterministic and periodic in the time domain, so they appear as line spectra in the frequency domain. Two types of spurious signals due to amplitude quantization are exactly formulated and compared in the time and frequency domains respectively. Then the frequency spectra and power levels of the spurious signals due to amplitude quantization in the absence of phase-accumulator truncation are emphatically analyzed, and the effects of the DDFS parameter variations on the spurious signals are thoroughly studied by computer simulation. And several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.展开更多
Using the Radon transform and morphological image processing, an algorithm for ship's wake detection in the SAR (synthetic aperture radar) image is developed. Being manipulated in the Radon space to invert the gra...Using the Radon transform and morphological image processing, an algorithm for ship's wake detection in the SAR (synthetic aperture radar) image is developed. Being manipulated in the Radon space to invert the gray-level and binary images, the linear texture of ship wake in oceanic clutter can be well detected. It has been applied to the automatic detection of a moving ship from the SEASAT SAR image. The results show that this algorithm is well robust in a strong noisy background and is not very sensitive to the threshold parameter and the working window size.展开更多
Time resolution of multipath delay profiles measured by using autocorrelation of pseudonoise (PN) code sequence is generally limited by the chip rate of the PN code sequence. In this paper, we propose a simple method ...Time resolution of multipath delay profiles measured by using autocorrelation of pseudonoise (PN) code sequence is generally limited by the chip rate of the PN code sequence. In this paper, we propose a simple method to improve the time resolution of delay profiles measured by the PN correlation method. Effectiveness of this method is demonstrated by indoor wireless propagation experiments.展开更多
Focused on the low noise figure requirements of erbium-doped preamplifiers, a two stage cascade preamplifier was presented based on the optimized design. With the total fiber length of 31.4 m and total pump power of 1...Focused on the low noise figure requirements of erbium-doped preamplifiers, a two stage cascade preamplifier was presented based on the optimized design. With the total fiber length of 31.4 m and total pump power of 135 mW, this preamplifier can produce above 30-dB gain and keep the noise figure below 4.76 dB for all C-band signals, with the minimum noise figure as low as 3.38 dB for-30-dBm, 1550-nm signal.展开更多
A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plu...A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit)stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.展开更多
基金supported by the National Grand Fundamental Research 973 Program of China(2004CB318109)the National High Technology Research and Development Program of China(863 Program)(2006AA01Z452).
文摘Spurious signals in direct digital frequency synthesizers (DDFSs) are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These signals are deterministic and periodic in the time domain, so they appear as line spectra in the frequency domain. Two types of spurious signals due to amplitude quantization are exactly formulated and compared in the time and frequency domains respectively. Then the frequency spectra and power levels of the spurious signals due to amplitude quantization in the absence of phase-accumulator truncation are emphatically analyzed, and the effects of the DDFS parameter variations on the spurious signals are thoroughly studied by computer simulation. And several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.
基金This project was supported by the National Natural Science Foundation of China (No. 49831060).
文摘Using the Radon transform and morphological image processing, an algorithm for ship's wake detection in the SAR (synthetic aperture radar) image is developed. Being manipulated in the Radon space to invert the gray-level and binary images, the linear texture of ship wake in oceanic clutter can be well detected. It has been applied to the automatic detection of a moving ship from the SEASAT SAR image. The results show that this algorithm is well robust in a strong noisy background and is not very sensitive to the threshold parameter and the working window size.
文摘Time resolution of multipath delay profiles measured by using autocorrelation of pseudonoise (PN) code sequence is generally limited by the chip rate of the PN code sequence. In this paper, we propose a simple method to improve the time resolution of delay profiles measured by the PN correlation method. Effectiveness of this method is demonstrated by indoor wireless propagation experiments.
文摘Focused on the low noise figure requirements of erbium-doped preamplifiers, a two stage cascade preamplifier was presented based on the optimized design. With the total fiber length of 31.4 m and total pump power of 135 mW, this preamplifier can produce above 30-dB gain and keep the noise figure below 4.76 dB for all C-band signals, with the minimum noise figure as low as 3.38 dB for-30-dBm, 1550-nm signal.
文摘A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit)stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.