The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization...The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.展开更多
The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of...The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of AES S-Box construction. The method reduces the steps needed to compute the multiplicative inverse, and computes the matrices multiplication used in this transformation, without a need to use the characteristic matrix, and the result is a modern method constructing the S-Box.展开更多
To obtain a low-power and compact implementation of the advanced encryption standard(AES)S-box,an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper.Inthe presented S-box,som...To obtain a low-power and compact implementation of the advanced encryption standard(AES)S-box,an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper.Inthe presented S-box,some improvements were made as follows.(1)Level-sensitive latches were insertedin data path to block the propagation Of the dynamic hazards,which lowered the power of data path cir-cuit.(2)Operations of latches were controlled by latch controllers based on presented asynchronous se-quence element:LC-element,which utilized static asymmetric C-element to construct a simple and pow-er-efficient circuit structure.(3)Implementation of the data path circuit was a semi-custom standard-cellcircuit on 0.25μm complementary mental oxide semiconductor(CMOS)process;and the full-custom de-sign methodology was adopted in the handshake circuit design.Experimental results show that the result-ing circuit achieves nearly 46% improvement with moderate area penalty(11.7%)compared with the re-lated composite field S-box in power performance.The presented S-box circuit can be a hardware intelli-gent property(IP)embedded in the targeted systems such as wireless sensor networks(WSN),smart-cams and radio frequency identification(RFID).展开更多
Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.Th...Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.The masking strategies in algorithm level view each S-Box as an independent moduleand mask them respectively,which are costly in size and power for non-linear characteristic of S-Boxes.The new method uses dynamic inhomogeneous S-Boxes instead of traditional homogeneous S-Boxes,andarranges the S-Boxes randomly.So the power and data path delay of substitution unit become unpre-dictable.The experimental results demonstrate that this scheme takes advantages of the circuit character-istics of various S-Box implementations to eliminate the correlation between crypto operation and power.Itneeds less extra circuits and suits resource constrained applications.展开更多
文摘The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.
文摘The substitution table (S-Box) of Advanced Encryption Standard (AES) and its properties are key elements in cryptanalysis ciphering. We aim here to propose a straightforward method for the non-linear transformation of AES S-Box construction. The method reduces the steps needed to compute the multiplicative inverse, and computes the matrices multiplication used in this transformation, without a need to use the characteristic matrix, and the result is a modern method constructing the S-Box.
基金the National High Technology Research and Development Programme of China(Grant No2006AA01Z226)the Project(Grant No2006Z001B)the Scientific Research Foundation of Huazhong University of Science and Technology
文摘To obtain a low-power and compact implementation of the advanced encryption standard(AES)S-box,an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper.Inthe presented S-box,some improvements were made as follows.(1)Level-sensitive latches were insertedin data path to block the propagation Of the dynamic hazards,which lowered the power of data path cir-cuit.(2)Operations of latches were controlled by latch controllers based on presented asynchronous se-quence element:LC-element,which utilized static asymmetric C-element to construct a simple and pow-er-efficient circuit structure.(3)Implementation of the data path circuit was a semi-custom standard-cellcircuit on 0.25μm complementary mental oxide semiconductor(CMOS)process;and the full-custom de-sign methodology was adopted in the handshake circuit design.Experimental results show that the result-ing circuit achieves nearly 46% improvement with moderate area penalty(11.7%)compared with the re-lated composite field S-box in power performance.The presented S-box circuit can be a hardware intelli-gent property(IP)embedded in the targeted systems such as wireless sensor networks(WSN),smart-cams and radio frequency identification(RFID).
基金the National High Technology Research and Development Programme of China(No.2006AA01Z226)
文摘Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.The masking strategies in algorithm level view each S-Box as an independent moduleand mask them respectively,which are costly in size and power for non-linear characteristic of S-Boxes.The new method uses dynamic inhomogeneous S-Boxes instead of traditional homogeneous S-Boxes,andarranges the S-Boxes randomly.So the power and data path delay of substitution unit become unpre-dictable.The experimental results demonstrate that this scheme takes advantages of the circuit character-istics of various S-Box implementations to eliminate the correlation between crypto operation and power.Itneeds less extra circuits and suits resource constrained applications.
