A Novel Sub-50nm Poly-Si Gate Patterning Technology

A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.

亚50 nm台阶高度标准物质的可控制备及定值研究

纳米台阶高度标准物质可以传递准确、可溯源的纳米高度量值。针对我国缺乏可控的高质量亚50 nm台阶高度标准物质制备技术的问题,提出了基于原子层沉积结合湿法刻蚀的纳米台阶高度标准物质研制方法,通过工艺过程优化实现了台阶高度亚纳米量级精确可控,制备出了最小公称高度仅为5 nm的亚50 nm台阶高度标准物质系列。其定值结果可溯源到米定义波长基准,扩展不确定度不超过2.0 nm,均匀性和稳定性较好,不同测试仪器一致性水平较高。研究结果表明,所研制的纳米台阶高度标准物质可以用于亚50 nm高度量值传递以及多种测量仪器之间量值的比对测量,其产业化批量生产的前景也将为半导体产业提供完善的计量保障。

向50nm拓进的光学光刻技术

非光学下一代光刻技术的缓慢进展和国际半导体技术发展规划 (ITRS)的加速 ,使光学光刻肩负着IC产业的重任 ,进一步向亚波长图形领域进军。为此 ,人们开发了大量的光学光刻扩展技术。其中包括传统的缩短波长和增大数值孔径 ,以及为了扩展最小间距线间图形的分辨力而提高部分相干性。通过这些途径 ,在 1 93nm曝光中实现了 >0 .80的数值孔径和0 .85的部分相干性 ,并将进一步向 1 57nm乃止 1 2 6nm过渡。此间 ,离轴照明 (OAI)、移相掩模(PSM)和光学邻近效应校正 (OPC)等K1因子将作为分辨力提高技术的核心 ,补充到光学光刻技术范畴。此外 ,光学光刻的扩展还将通过像场尺寸缩小和倍率增大的方法使步进扫描光刻机更好地支持并可望进入至少 70nm的技术节点 ,乃至 50nm的下一代光刻。

50nmSOI-DTMOS器件的性能

利用二维器件模拟软件ISE对 5 0nm沟道长度下SOI DTMOS器件性能进行了研究 ,并与常规结构的SOI器件作了比较 .结果表明 ,在 5 0nm沟长下 ,SOI DTMOS器件性能远远优于常规SOI器件 .SOI DTMOS器件具有更好的亚阈值特性 ,其亚阈值泄漏电流比常规SOI器件小 2～ 3个数量级 ,从而使其具有更低的静态功耗 .同时 ,SOI DTMOS器件较高的驱动电流保证了管子的工作速度 ,并且较常规SOI器件能更有效地抑制短沟道器件的穿通效应、DIBL及SCE效应 ,从而保证了在尺寸进一步减小的情况下管子的性能 .对SOI DTMOS器件的物理机制进行了初步分析 ,揭示了其性能远优于常规结构的物理本质 ,同时也指出了进一步研究的方向 .

Sub-10 nm fabrication:methods and applications

Reliable fabrication of micro/nanostructures with sub-10 nm features is of great significance for advancing nanoscience and nanotechnology.While the capability of current complementary metal-oxide semiconductor(CMOS)chip manufacturing can produce structures on the sub-10 nm scale,many emerging applications,such as nano-optics,biosensing,and quantum devices,also require ultrasmall features down to single digital nanometers.In these emerging applications,CMOS-based manufacturing methods are currently not feasible or appropriate due to the considerations of usage cost,material compatibility,and exotic features.Therefore,several specific methods have been developed in the past decades for different applications.In this review,we attempt to give a systematic summary on sub-10 nm fabrication methods and their related applications.In the first and second parts,we give a brief introduction of the background of this research topic and explain why sub-10 nm fabrication is interesting from both scientific and technological perspectives.In the third part,we comprehensively summarize the fabrication methods and classify them into three main approaches,including lithographic,mechanics-enabled,and post-trimming processes.The fourth part discusses the applications of these processes in quantum devices,nano-optics,and high-performance sensing.Finally,a perspective is given to discuss the challenges and opportunities associated with this research topic.

Nanofabrication of 50 nm zone plates through e-beam lithography with local proximity effect correction for x-ray imaging

High resolution Fresnel zone plates for nanoscale three-dimensional imaging of materials by both soft and hard x-rays are increasingly needed by the broad applications in nanoscience and nanotechnology.When the outmost zone-width is shrinking down to 50 nm or even below,patterning the zone plates with high aspect ratio by electron beam lithography still remains a challenge because of the proximity effect.The uneven charge distribution in the exposed resist is still frequently observed even after standard proximity effect correction(PEC),because of the large variety in the line width.This work develops a new strategy,nicknamed as local proximity effect correction(LPEC),efficiently modifying the deposited energy over the whole zone plate on the top of proximity effect correction.By this way,50 nm zone plates with the aspect ratio from 4:1 up to 15:1 and the duty cycle close to 0.5 have been fabricated.Their imaging capability in soft(1.3 keV)and hard(9 keV)x-ray,respectively,has been demonstrated in Shanghai Synchrotron Radiation Facility(SSRF)with the resolution of 50 nm.The local proximity effect correction developed in this work should also be generally significant for the generation of zone plates with high resolutions beyond 50 nm.

Directed self-assembly of block copolymers for sub-10 nm fabrication

Directed self-assembly(DSA)emerges as one of the most promising new patterning techniques for single digit miniaturization and next generation lithography.DSA achieves high-resolution patterning by molecular assembly that circumvents the diffraction limit of conventional photolithography.Recently,the International Roadmap for Devices and Systems listed DSA as one of the advanced lithography techniques for the fabrication of 3-5 nm technology node devices.DSA can be combined with other lithography techniques,such as extreme ultra violet(EUV)and 193 nm immersion(193i),to further enhance the patterning resolution and the device density.So far,DSA has demonstrated its superior ability for the fabrication of nanoscale devices,such as fin field effect transistor and bit pattern media,offering a variety of configurations for high-density integration and low-cost manufacturing.Over 1 T in-2 device density can be achieved either by direct templating or coupled with nanoimprinting to improve the throughput.The development of high x block copolymer further enhances the patterning resolution of DSA.In addition to its superiority in high-resolution patterning,the implementation ofDSA on a 300 mm pivot line fully demonstrates its potential for large-scale,high-throughput,and cost-effective manufacturing in industrial environment.

Vertical MBE growth of Si fins on sub-10 nm patterned substrate for high-performance FinFET technology

A high quality epitaxial Si layer by molecular beam epitaxy(MBE)on Si(001)substrates was demonstrated to fabricate a channel with low density defects for high-performance Fin FET technology.In order to study the effects of fin width and crystallography orientation on the MBE behavior,a 30 nm thick Si layer was deposited on the top of an etched Si fin with different widths from 10 nm to 50 nm and orientations of 100 and 110.The result shows that a defect-free Si film was obtained on the fin by MBE,since the etching damage was confined in the bottom of the epitaxial layer.In addition,the vertical growth of the epitaxial Si layer was observed on sub-10 nm 100 Si fins,and this was explained by a kinetic mechanism.

Achieving a sub-10 nm nanopore array in silicon by metal-assisted chemical etching and machine learning

Solid-state nanopores with controllable pore size and morphology have huge application potential.However,it has been very challenging to process sub-10 nm silicon nanopore arrays with high efficiency and high quality at low cost.In this study,a method combining metal-assisted chemical etching and machine learning is proposed to fabricate sub-10 nm nanopore arrays on silicon wafers with various dopant types and concentrations.Through a SVM algorithm,the relationship between the nanopore structures and the fabrication conditions,including the etching solution,etching time,dopant type,and concentration,was modeled and experimentally verified.Based on this,a processing parameter window for generating regular nanopore arrays on silicon wafers with variable doping types and concentrations was obtained.The proposed machine-learning-assisted etching method will provide a feasible and economical way to process high-quality silicon nanopores,nanostructures,and devices.

工程机械耐磨钢NM50CrVA的热处理与组织性能

本文主要针对淬回火对传统热轧和薄板坯连铸连轧工程机械NM50CrVA耐磨钢板显微组织以及力学性能的影响进行了研究,并对连铸连轧NM50CrVA和传统热轧Q355、30CrMoA以及1045钢板的耐磨性能进行了综合的分析。

50nm Nor Flash中的B/S Deposition用Normal Cu替代RFxCu工艺研究

阐述如何使用NormalCu机型来沉积小线宽50nm产品的Barrier&Seed层,通过调制偏压电压及时间,改善了台阶覆盖性,避免了小线宽产品在开口处overhang的形成,提升了Normal机型工艺极限。使得制品缺陷、电性、良率和可靠性与RFx Cu机型在最终的产品性能上表现一致,在50nm Nor Flash平台上顺利量产使用。

工程机械耐磨钢NM50CrVA的热处理与组织性能

研究了淬回火对薄板坯连铸连轧和传统热轧工程机械NM50CrVA耐磨钢板显微组织和力学性能的影响,并对比分析了连铸连轧NM50CrVA与传统热轧Q355、30CrMoA和1045钢板的耐磨性能。结果表明,连铸连轧NM50CrVA钢的组织为铁素体+层片状珠光体,回火后组织为回火马氏体+少量铁素体,而传统热轧态NM50CrVA钢的组织为粒状珠光体+铁素体,回火后组织为回火马氏体;在相同淬火与回火工艺下,连铸连轧态NM50CrVA钢的强度增加幅度更大,且相同状态下连铸连轧NM50CrVA钢的强度更高而塑性相当。在相同磨料磨损条件下,磨损质量损失从大至小顺序为Q355>30CrMoA>1045>NM50CrVA钢,NM50CrVA、1045和30CrMoA钢的相对耐磨性分别为1.99、1.21和1.14,NM50CrVA钢具有最佳的耐磨性;1045、30CrMoA和Q355钢的主要磨损机制为犁沟和显微切削,NM50CrVA钢的主要磨损机制为疲劳剥落磨损。

制备MnO纳米颗粒的新方法

以碳酸锰在氩气中的热重分析为理论依据,利用X射线衍射、扫描电子显微镜和高分辨透射电子显微镜对碳酸锰在氩气中热分解最终产物进行分析.研究结果表明：碳酸锰在氩气中的热分解过程可以分为：（1）在300℃前,碳酸锰的质量损率失约7.5%,此过程是碳酸锰因受热而失去吸附水或者结晶水;（2）在300-500℃之间,失去吸附水或者结晶水的样品质量损失率最大,其质量损失率约为30%,其热分解产物为粒径约为50 nm左右的MnO球形颗粒.

考虑二维量子力学效应的MOSFET解析电荷模型

在亚 5 0 nm的 MOSFET中 ,沿沟道方向上的量子力学效应对器件特性有很大的影响。基于 WKB理论 ,考虑MOSFET中该效应对垂直沟道方向上能级的影响 ,引入了其对于阈电压的修正。在此基础上 ,对沟道方向的子带作了抛物线近似 ,从而建立了一个考虑二维量子力学的电荷解析模型。根据该模型 ,得到二维量子力学修正和沟道长度以及其他工艺参数的关系。与数值模拟结果的比较表明 ,该解析模型的精度令人满意 ,并且得出以下结论 :二维量子力学效应使阈电压下降 ,并且在亚 5 0 nm的 MOSFET中 ,这个修正不可忽略。

Super-aligned films of sub-1 nm Bi_(2)O_(3)-polyoxometalate nanowires as interlayers in lithiumsulfur batteries

Sub-1 nm nanowires(SNWs) can not only be processed like polymers due to their polymer-analogue properties but also show multifunctions owing to their well-manipulated compositions and structures. Rationally designed and engineered multicomponent heterostructure SNWs can further enhance their multifunction performance while it is very challenging to achieve such SNWs at sub-nanoscale.Herein, we synthesized Bi_(2)O_(3)-polyoxometalate heterostructure SNWs(PMB SNWs), and fabricated super-aligned PMB SNWs films(S-PMB SNWs films), which can serve as interlayers to efficiently suppress lithium polysulfide(LPS)shuttling, intrinsically promote the redox kinetics of the LPS conversion and substantially protect the Li anode. The lithium-sulfur(Li-S) battery with the S-PMB SNWs film as the interlayer showcases an ultralow capacity decay rate with 0.013% per cycle over 850 cycles. This study demonstrates the potential of heterostructure SNWs to improve the performance of Li-S batteries.

基于CMOS集成温度传感器的电路设计与仿真

为提高温度传感器的测量精度,同时缩小其面积和功耗,文中设计了一种使用NPN晶体管进行温度测量的完全集成互补型金属氧化物半导体传感器。该传感器主要由偏置电路,运算放大器和热传感器电路组成。偏置电路为传感器提供偏置条件,其由启动电路和β乘法器电路组成。文中采用LTspice and Matlab进行电路设计,并在50 nm工艺下对传感器电路进行仿真,得到所设计的温度传感器在-30~125℃范围内,温度系数为5.9 m V/℃。

二维量子力学效应对阈值电压的影响

在亚50nm的MOSFET中,沿沟道方向的量子力学效应严重影响了器件性能.基于WKB理论,考虑MOSFET中该效应对垂直沟道方向上能级的影响,引入了其时阈值电压的修正.继而对沟道方向的子带作了抛物线近似并进行了数值拟合,从而建立了一个考虑量子力学效应的全解析模型.由此模型可以得到二维量子力学修正和沟道长度以及其它器件参数的关系.与数值模拟结构比较可以得出如下结论:在亚50nm的MOSFET中,量子力学效应引入了阈值电压的修正是不可忽略的.且此全解析模型精度令人满意.

喷油参数对重型柴油机细小颗粒排放的影响

在满足国六排放重型柴油机上,分别测试了不同EGR开度、轨压、主喷提前角和后喷油量对发动机原排PN排放的影响,同时基于国六标准WHTC循环分析了PN的排放特征,结果表明:不同喷油参数下,PN10和PN23排放规律表现一致,在高负荷区域,随EGR率的增加,sub-23nm占比逐渐降低;EGR率在一定范围内,主喷提前角的增加并未影响sub-23nm占比变化,同时发现不同工况下sub-23nm占比基本在10%~34.1%;随轨压的增加,sub-23nm的占比增大;在低速低负荷区域,随后喷油量的增加,sub-23nm占比呈先增加后降低的趋势。在循环排放方面,原排的冷热态WHTC循环下PN10和PN23排放相当,热态WHTC循环下喷射尿素会增加PN的排放,其中sub-23nm增加了8.34倍。

Generation of sub-100 fs pulses tunable from 1700 to 2100 nm from a compact frequency-shifted Er-fiber laser

We report generation of sub-100 fs pulses tunable from 1700 to 2100 nm via Raman soliton self-frequency shift.The nonlinear shift occurs in a highly nonlinear fiber, which is pumped by an Er-doped fiber laser. The whole system is fully fiberized, without the use of any free-space optics. Thanks to its exceptional simplicity, the setup can be considered as an alternative to mode-locked Tm-and Ho-doped fiber lasers.

宣化热电#1、#2机组低氮燃烧器改造

河北省环保厅根据申奥工作需要下发了新的环保要求,张家口地区燃煤电厂烟气氮氧化物自2015年11月1日必须达到50mg/m3以下的排放要求。河北建投宣化热电有限责任公司2×300MW机组改造前NOx排放量控制在100mg/m3以下,不能满足50mg/m3以下的新排放标准,需对燃烧系统进行低氮燃烧改造,实现更加深度的分级燃烧,达到降低NOx排放值的目的。