Reliable fabrication of micro/nanostructures with sub-10 nm features is of great significance for advancing nanoscience and nanotechnology.While the capability of current complementary metal-oxide semiconductor(CMOS)c...Reliable fabrication of micro/nanostructures with sub-10 nm features is of great significance for advancing nanoscience and nanotechnology.While the capability of current complementary metal-oxide semiconductor(CMOS)chip manufacturing can produce structures on the sub-10 nm scale,many emerging applications,such as nano-optics,biosensing,and quantum devices,also require ultrasmall features down to single digital nanometers.In these emerging applications,CMOS-based manufacturing methods are currently not feasible or appropriate due to the considerations of usage cost,material compatibility,and exotic features.Therefore,several specific methods have been developed in the past decades for different applications.In this review,we attempt to give a systematic summary on sub-10 nm fabrication methods and their related applications.In the first and second parts,we give a brief introduction of the background of this research topic and explain why sub-10 nm fabrication is interesting from both scientific and technological perspectives.In the third part,we comprehensively summarize the fabrication methods and classify them into three main approaches,including lithographic,mechanics-enabled,and post-trimming processes.The fourth part discusses the applications of these processes in quantum devices,nano-optics,and high-performance sensing.Finally,a perspective is given to discuss the challenges and opportunities associated with this research topic.展开更多
High resolution Fresnel zone plates for nanoscale three-dimensional imaging of materials by both soft and hard x-rays are increasingly needed by the broad applications in nanoscience and nanotechnology.When the outmos...High resolution Fresnel zone plates for nanoscale three-dimensional imaging of materials by both soft and hard x-rays are increasingly needed by the broad applications in nanoscience and nanotechnology.When the outmost zone-width is shrinking down to 50 nm or even below,patterning the zone plates with high aspect ratio by electron beam lithography still remains a challenge because of the proximity effect.The uneven charge distribution in the exposed resist is still frequently observed even after standard proximity effect correction(PEC),because of the large variety in the line width.This work develops a new strategy,nicknamed as local proximity effect correction(LPEC),efficiently modifying the deposited energy over the whole zone plate on the top of proximity effect correction.By this way,50 nm zone plates with the aspect ratio from 4:1 up to 15:1 and the duty cycle close to 0.5 have been fabricated.Their imaging capability in soft(1.3 keV)and hard(9 keV)x-ray,respectively,has been demonstrated in Shanghai Synchrotron Radiation Facility(SSRF)with the resolution of 50 nm.The local proximity effect correction developed in this work should also be generally significant for the generation of zone plates with high resolutions beyond 50 nm.展开更多
Directed self-assembly(DSA)emerges as one of the most promising new patterning techniques for single digit miniaturization and next generation lithography.DSA achieves high-resolution patterning by molecular assembly ...Directed self-assembly(DSA)emerges as one of the most promising new patterning techniques for single digit miniaturization and next generation lithography.DSA achieves high-resolution patterning by molecular assembly that circumvents the diffraction limit of conventional photolithography.Recently,the International Roadmap for Devices and Systems listed DSA as one of the advanced lithography techniques for the fabrication of 3-5 nm technology node devices.DSA can be combined with other lithography techniques,such as extreme ultra violet(EUV)and 193 nm immersion(193i),to further enhance the patterning resolution and the device density.So far,DSA has demonstrated its superior ability for the fabrication of nanoscale devices,such as fin field effect transistor and bit pattern media,offering a variety of configurations for high-density integration and low-cost manufacturing.Over 1 T in-2 device density can be achieved either by direct templating or coupled with nanoimprinting to improve the throughput.The development of high x block copolymer further enhances the patterning resolution of DSA.In addition to its superiority in high-resolution patterning,the implementation ofDSA on a 300 mm pivot line fully demonstrates its potential for large-scale,high-throughput,and cost-effective manufacturing in industrial environment.展开更多
A high quality epitaxial Si layer by molecular beam epitaxy(MBE)on Si(001)substrates was demonstrated to fabricate a channel with low density defects for high-performance Fin FET technology.In order to study the effec...A high quality epitaxial Si layer by molecular beam epitaxy(MBE)on Si(001)substrates was demonstrated to fabricate a channel with low density defects for high-performance Fin FET technology.In order to study the effects of fin width and crystallography orientation on the MBE behavior,a 30 nm thick Si layer was deposited on the top of an etched Si fin with different widths from 10 nm to 50 nm and orientations of 100 and 110.The result shows that a defect-free Si film was obtained on the fin by MBE,since the etching damage was confined in the bottom of the epitaxial layer.In addition,the vertical growth of the epitaxial Si layer was observed on sub-10 nm 100 Si fins,and this was explained by a kinetic mechanism.展开更多
Solid-state nanopores with controllable pore size and morphology have huge application potential.However,it has been very challenging to process sub-10 nm silicon nanopore arrays with high efficiency and high quality ...Solid-state nanopores with controllable pore size and morphology have huge application potential.However,it has been very challenging to process sub-10 nm silicon nanopore arrays with high efficiency and high quality at low cost.In this study,a method combining metal-assisted chemical etching and machine learning is proposed to fabricate sub-10 nm nanopore arrays on silicon wafers with various dopant types and concentrations.Through a SVM algorithm,the relationship between the nanopore structures and the fabrication conditions,including the etching solution,etching time,dopant type,and concentration,was modeled and experimentally verified.Based on this,a processing parameter window for generating regular nanopore arrays on silicon wafers with variable doping types and concentrations was obtained.The proposed machine-learning-assisted etching method will provide a feasible and economical way to process high-quality silicon nanopores,nanostructures,and devices.展开更多
阐述如何使用NormalCu机型来沉积小线宽50nm产品的Barrier&Seed层,通过调制偏压电压及时间,改善了台阶覆盖性,避免了小线宽产品在开口处overhang的形成,提升了Normal机型工艺极限。使得制品缺陷、电性、良率和可靠性与RFx Cu机型在...阐述如何使用NormalCu机型来沉积小线宽50nm产品的Barrier&Seed层,通过调制偏压电压及时间,改善了台阶覆盖性,避免了小线宽产品在开口处overhang的形成,提升了Normal机型工艺极限。使得制品缺陷、电性、良率和可靠性与RFx Cu机型在最终的产品性能上表现一致,在50nm Nor Flash平台上顺利量产使用。展开更多
为提高温度传感器的测量精度,同时缩小其面积和功耗,文中设计了一种使用NPN晶体管进行温度测量的完全集成互补型金属氧化物半导体传感器。该传感器主要由偏置电路,运算放大器和热传感器电路组成。偏置电路为传感器提供偏置条件,其由启...为提高温度传感器的测量精度,同时缩小其面积和功耗,文中设计了一种使用NPN晶体管进行温度测量的完全集成互补型金属氧化物半导体传感器。该传感器主要由偏置电路,运算放大器和热传感器电路组成。偏置电路为传感器提供偏置条件,其由启动电路和β乘法器电路组成。文中采用LTspice and Matlab进行电路设计,并在50 nm工艺下对传感器电路进行仿真,得到所设计的温度传感器在-30~125℃范围内,温度系数为5.9 m V/℃。展开更多
We report generation of sub-100 fs pulses tunable from 1700 to 2100 nm via Raman soliton self-frequency shift.The nonlinear shift occurs in a highly nonlinear fiber, which is pumped by an Er-doped fiber laser. The who...We report generation of sub-100 fs pulses tunable from 1700 to 2100 nm via Raman soliton self-frequency shift.The nonlinear shift occurs in a highly nonlinear fiber, which is pumped by an Er-doped fiber laser. The whole system is fully fiberized, without the use of any free-space optics. Thanks to its exceptional simplicity, the setup can be considered as an alternative to mode-locked Tm-and Ho-doped fiber lasers.展开更多
Patterned nanostructures with ultrasmall features endow functional devices with unique nanoconfinement and performance enhancements.The increasing demand for miniaturization has stimulated the development of sub-100 n...Patterned nanostructures with ultrasmall features endow functional devices with unique nanoconfinement and performance enhancements.The increasing demand for miniaturization has stimulated the development of sub-100 nm nanopatterning techniques.Beyond conventional lithography—which is limited by unavoidable factors—advanced patterning techniques have been reported to produce nanoscale features down to molecular or even atomic scale.In this review,unconventional techniques for sub-100 nm nanopatterning are discussed,in particular the principles by which to achieve the desired patterns(among other important issues).Such techniques can be classified into three categories:template-replica,template-induced,and template-free techniques.Moreover,multi-dimensional nanostructures consist of various building materials,the unique properties of which are summarized.Finally,the remaining challenges and opportunities for large-scale patterning,the improvement of device perfor-mance,the multi-dimensional nanostructures of biocompatible materials,molecular-scale patterning,and the carbon footprint requirements for future nanofabrication processes are discussed.展开更多
基金supported by the National Natural Science Foundation of China(Grants Nos.51722503,51805160and U1930114)the National Key Research and Development Program of China(Grant No.2018YFE0109200)the Guangdong Basic Research Foundation(Grant No.2020A1515110971)。
文摘Reliable fabrication of micro/nanostructures with sub-10 nm features is of great significance for advancing nanoscience and nanotechnology.While the capability of current complementary metal-oxide semiconductor(CMOS)chip manufacturing can produce structures on the sub-10 nm scale,many emerging applications,such as nano-optics,biosensing,and quantum devices,also require ultrasmall features down to single digital nanometers.In these emerging applications,CMOS-based manufacturing methods are currently not feasible or appropriate due to the considerations of usage cost,material compatibility,and exotic features.Therefore,several specific methods have been developed in the past decades for different applications.In this review,we attempt to give a systematic summary on sub-10 nm fabrication methods and their related applications.In the first and second parts,we give a brief introduction of the background of this research topic and explain why sub-10 nm fabrication is interesting from both scientific and technological perspectives.In the third part,we comprehensively summarize the fabrication methods and classify them into three main approaches,including lithographic,mechanics-enabled,and post-trimming processes.The fourth part discusses the applications of these processes in quantum devices,nano-optics,and high-performance sensing.Finally,a perspective is given to discuss the challenges and opportunities associated with this research topic.
基金Project supported by the National Natural Science Foundation of China(Grant No.U1732104)China Postdoctoral Science Foundation(Grant No.2017M611443)Shanghai STCSM2019-11-20 Grant,China(Grant No.19142202700)。
文摘High resolution Fresnel zone plates for nanoscale three-dimensional imaging of materials by both soft and hard x-rays are increasingly needed by the broad applications in nanoscience and nanotechnology.When the outmost zone-width is shrinking down to 50 nm or even below,patterning the zone plates with high aspect ratio by electron beam lithography still remains a challenge because of the proximity effect.The uneven charge distribution in the exposed resist is still frequently observed even after standard proximity effect correction(PEC),because of the large variety in the line width.This work develops a new strategy,nicknamed as local proximity effect correction(LPEC),efficiently modifying the deposited energy over the whole zone plate on the top of proximity effect correction.By this way,50 nm zone plates with the aspect ratio from 4:1 up to 15:1 and the duty cycle close to 0.5 have been fabricated.Their imaging capability in soft(1.3 keV)and hard(9 keV)x-ray,respectively,has been demonstrated in Shanghai Synchrotron Radiation Facility(SSRF)with the resolution of 50 nm.The local proximity effect correction developed in this work should also be generally significant for the generation of zone plates with high resolutions beyond 50 nm.
文摘Directed self-assembly(DSA)emerges as one of the most promising new patterning techniques for single digit miniaturization and next generation lithography.DSA achieves high-resolution patterning by molecular assembly that circumvents the diffraction limit of conventional photolithography.Recently,the International Roadmap for Devices and Systems listed DSA as one of the advanced lithography techniques for the fabrication of 3-5 nm technology node devices.DSA can be combined with other lithography techniques,such as extreme ultra violet(EUV)and 193 nm immersion(193i),to further enhance the patterning resolution and the device density.So far,DSA has demonstrated its superior ability for the fabrication of nanoscale devices,such as fin field effect transistor and bit pattern media,offering a variety of configurations for high-density integration and low-cost manufacturing.Over 1 T in-2 device density can be achieved either by direct templating or coupled with nanoimprinting to improve the throughput.The development of high x block copolymer further enhances the patterning resolution of DSA.In addition to its superiority in high-resolution patterning,the implementation ofDSA on a 300 mm pivot line fully demonstrates its potential for large-scale,high-throughput,and cost-effective manufacturing in industrial environment.
基金the National Key Research and Development Program of China(Grant No.2016YFA0200504)the National Natural Science Foundation of China(Grant No.61927901)。
文摘A high quality epitaxial Si layer by molecular beam epitaxy(MBE)on Si(001)substrates was demonstrated to fabricate a channel with low density defects for high-performance Fin FET technology.In order to study the effects of fin width and crystallography orientation on the MBE behavior,a 30 nm thick Si layer was deposited on the top of an etched Si fin with different widths from 10 nm to 50 nm and orientations of 100 and 110.The result shows that a defect-free Si film was obtained on the fin by MBE,since the etching damage was confined in the bottom of the epitaxial layer.In addition,the vertical growth of the epitaxial Si layer was observed on sub-10 nm 100 Si fins,and this was explained by a kinetic mechanism.
基金supported by the National Natural Science Foundation of China[Grant Nos.51975127,U20A6004]the Guangdong-Hong Kong Technology Coopeartion[Grant No.GHP/112/19GD]from Hong Kong Innovation and Technology Commission+1 种基金Research and Development Program of Guangdong Province[Grant No.2020A0505140008]the Fund of Key-Area Research and Development Program of Guangdong Province[Grant No.2018B090906002]。
文摘Solid-state nanopores with controllable pore size and morphology have huge application potential.However,it has been very challenging to process sub-10 nm silicon nanopore arrays with high efficiency and high quality at low cost.In this study,a method combining metal-assisted chemical etching and machine learning is proposed to fabricate sub-10 nm nanopore arrays on silicon wafers with various dopant types and concentrations.Through a SVM algorithm,the relationship between the nanopore structures and the fabrication conditions,including the etching solution,etching time,dopant type,and concentration,was modeled and experimentally verified.Based on this,a processing parameter window for generating regular nanopore arrays on silicon wafers with variable doping types and concentrations was obtained.The proposed machine-learning-assisted etching method will provide a feasible and economical way to process high-quality silicon nanopores,nanostructures,and devices.
文摘阐述如何使用NormalCu机型来沉积小线宽50nm产品的Barrier&Seed层,通过调制偏压电压及时间,改善了台阶覆盖性,避免了小线宽产品在开口处overhang的形成,提升了Normal机型工艺极限。使得制品缺陷、电性、良率和可靠性与RFx Cu机型在最终的产品性能上表现一致,在50nm Nor Flash平台上顺利量产使用。
文摘为提高温度传感器的测量精度,同时缩小其面积和功耗,文中设计了一种使用NPN晶体管进行温度测量的完全集成互补型金属氧化物半导体传感器。该传感器主要由偏置电路,运算放大器和热传感器电路组成。偏置电路为传感器提供偏置条件,其由启动电路和β乘法器电路组成。文中采用LTspice and Matlab进行电路设计,并在50 nm工艺下对传感器电路进行仿真,得到所设计的温度传感器在-30~125℃范围内,温度系数为5.9 m V/℃。
基金Narodowe Centrum Nauki(NCN)(2014/13/D/ST7/02090,2014/13/D/ST7/02143)Wroclaw University of Science and Technology(0401/0094/16)
文摘We report generation of sub-100 fs pulses tunable from 1700 to 2100 nm via Raman soliton self-frequency shift.The nonlinear shift occurs in a highly nonlinear fiber, which is pumped by an Er-doped fiber laser. The whole system is fully fiberized, without the use of any free-space optics. Thanks to its exceptional simplicity, the setup can be considered as an alternative to mode-locked Tm-and Ho-doped fiber lasers.
基金Beijing National Laboratory for Molecular Sciences,Grant/Award Numbers:2019BMS20003,BNLMS-CXXM-202005CAS-VPST Silk Road Science Fund 2022,Grant/Award Number:121111KYSB20210006+3 种基金K.C.Wong Education Foundation,China Postdoctoral Science Foundation,Grant/Award Number:2020M670466External Cooperation Program of Chinese Academy of Sciences,Grant/Award Number:GJHZ201948the National Key R&D Program of China,Grant/Award Numbers:2018YFA0208501,2018YFA0703200the National Nature Science Foundation of China,Grant/Award Numbers:22002171,22175185,51773206,51803217,51961145102,52003273,52003276,91963212。
文摘Patterned nanostructures with ultrasmall features endow functional devices with unique nanoconfinement and performance enhancements.The increasing demand for miniaturization has stimulated the development of sub-100 nm nanopatterning techniques.Beyond conventional lithography—which is limited by unavoidable factors—advanced patterning techniques have been reported to produce nanoscale features down to molecular or even atomic scale.In this review,unconventional techniques for sub-100 nm nanopatterning are discussed,in particular the principles by which to achieve the desired patterns(among other important issues).Such techniques can be classified into three categories:template-replica,template-induced,and template-free techniques.Moreover,multi-dimensional nanostructures consist of various building materials,the unique properties of which are summarized.Finally,the remaining challenges and opportunities for large-scale patterning,the improvement of device perfor-mance,the multi-dimensional nanostructures of biocompatible materials,molecular-scale patterning,and the carbon footprint requirements for future nanofabrication processes are discussed.