Pattern imprinting in deep sub-micron static random access memories induced by total dose irradiation

Pattem imprinting in deep sub-micron static random access memories （SRAMs） during total dose irradiation is inves- tigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiation is gradually imprinted on their background data pattern. We build a relationship between the memory cell＇s static noise margin （SNM） and the background data, and study the influence of irradiation on the probability density function of ASNM, which is the difference between two data sides＇ SNMs, to discuss the reason for pattern imprinting. Finally, we demonstrate that, for micron and deep sub-micron devices, the mechanism of pattern imprinting is the bias-dependent threshold shift of the transistor, but for a deep sub-micron device the shift results from charge trapping in the shallow trench isolation （STI） oxide rather than from the gate oxide of the micron-device.

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET's

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is consideredas the most promising candidate used in deep and super-deep sub-micron region, for it cansuppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energytransport model, using two-dimensional device simulator Medici, the relation between structureparameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studiedand compared with that of counterpart conventional planar device in this paper. The examinedstructure parameters include negative junction depth, concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect deeply even indeep sub-micron region. The studies also indicate that hot carrier effect is strongly influencedby the concave corner and channel length for grooved gate device. With the increase of concavecorner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the reducingof effective channel length, the hot carrier effect becomes large.

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.