A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface pote...A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.展开更多
A 0. 1μm SOI grooved gate pMOSFET with 5.6nm gate oxide is fabricated and demonstrated. The groove depth is 180nm. The transfer characteristics and the output characteristics are shown. At Vds = -1. 5V,the drain satu...A 0. 1μm SOI grooved gate pMOSFET with 5.6nm gate oxide is fabricated and demonstrated. The groove depth is 180nm. The transfer characteristics and the output characteristics are shown. At Vds = -1. 5V,the drain saturation current is 380μA and the off-state leakage current is 1.9nA;the sub-threshold slope is 115mV/dec at Vds = -0. 1V and DIBL factor is 70. 7mV/V. The electrical characteristic comparison between the 0.1μm SOI groovedgate pMOSFET and the 0. 1μm bulk grooved gate one with the same process demonstrates that a 0. 1μm SOI grooved gate pMOSFET has better characteristics in current-driving capability and sub-threshold slope.展开更多
The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several...The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several effective approaches have been proposed based on a numerical insight into the working mechanism of T-CNFETs：tuning the doping level of source/drain leads,minimizing the quantum capacitance value via tuning the bias condition or increasing the insulator capacitance,and adopting a staircase doping strategy in the drain lead.Non-equilibrium Green＇s function based simulation results show that all these approaches can contribute to a smaller average inverse sub-threshold slope, which is quite desirable in high-frequency or low-power applications.展开更多
A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor（SG-JLTFET） has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped chann...A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor（SG-JLTFET） has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped channel of GaSb i.e.gallium antimonide which is grown epitaxially over silicon substrate.The DC performance parameters such as I（on）,I（on）/I（off）,average and point subthreshold slope as well as device parameters for analog applications viz.transconductance gm,transconductance generation efficiency gm/ID,various capacitances and the unity gain frequency fT are studied using a device simulator.Along with examining its endurance to short channel effects,the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET（DG-JLTFET）.The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.展开更多
For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute devic...For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.展开更多
Due to carrier band-to-band-tunneling （BTBT） through channel-source/drain contacts, conventional MOS- like Carbon Nanotube Field Effect Transistors （C-CNFETs） suffer from ambipolar conductance, which deteriorates ...Due to carrier band-to-band-tunneling （BTBT） through channel-source/drain contacts, conventional MOS- like Carbon Nanotube Field Effect Transistors （C-CNFETs） suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed and all kinds of source/drain contacting conditions are considered in this paper. The non-equilibrium Green＇s function （NEGF） formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold perfor- mance, even with source/drain contacts being of Schottky type. And these are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends strongly on the choice of tuning voltage value, which should be paid much attention to obtain a proper trade-off between power and speed in application.展开更多
An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performanc...An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET （DG-IMOS） is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG （dual material gate） DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better IoN, ION/IoFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized perform- ance is achieved including ION/IoFF ratio of 2.87 × 10^9 A/μm with/ON as 11.87 × 10^-4 A/μm and transconductance of 1.06× 10^-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.展开更多
文摘A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.
文摘A 0. 1μm SOI grooved gate pMOSFET with 5.6nm gate oxide is fabricated and demonstrated. The groove depth is 180nm. The transfer characteristics and the output characteristics are shown. At Vds = -1. 5V,the drain saturation current is 380μA and the off-state leakage current is 1.9nA;the sub-threshold slope is 115mV/dec at Vds = -0. 1V and DIBL factor is 70. 7mV/V. The electrical characteristic comparison between the 0.1μm SOI groovedgate pMOSFET and the 0. 1μm bulk grooved gate one with the same process demonstrates that a 0. 1μm SOI grooved gate pMOSFET has better characteristics in current-driving capability and sub-threshold slope.
基金supported by the Hi-Tech Research and Development Program of China(No.2009AA01Z114)
文摘The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several effective approaches have been proposed based on a numerical insight into the working mechanism of T-CNFETs：tuning the doping level of source/drain leads,minimizing the quantum capacitance value via tuning the bias condition or increasing the insulator capacitance,and adopting a staircase doping strategy in the drain lead.Non-equilibrium Green＇s function based simulation results show that all these approaches can contribute to a smaller average inverse sub-threshold slope, which is quite desirable in high-frequency or low-power applications.
文摘A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor（SG-JLTFET） has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped channel of GaSb i.e.gallium antimonide which is grown epitaxially over silicon substrate.The DC performance parameters such as I（on）,I（on）/I（off）,average and point subthreshold slope as well as device parameters for analog applications viz.transconductance gm,transconductance generation efficiency gm/ID,various capacitances and the unity gain frequency fT are studied using a device simulator.Along with examining its endurance to short channel effects,the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET（DG-JLTFET）.The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.
文摘For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.
基金Project supported by the National High-Tech Research & Development Program of China(Nos.2009AA01Z124,2009AA01Z114)
文摘Due to carrier band-to-band-tunneling （BTBT） through channel-source/drain contacts, conventional MOS- like Carbon Nanotube Field Effect Transistors （C-CNFETs） suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed and all kinds of source/drain contacting conditions are considered in this paper. The non-equilibrium Green＇s function （NEGF） formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold perfor- mance, even with source/drain contacts being of Schottky type. And these are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends strongly on the choice of tuning voltage value, which should be paid much attention to obtain a proper trade-off between power and speed in application.
文摘An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET （DG-IMOS） is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG （dual material gate） DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better IoN, ION/IoFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized perform- ance is achieved including ION/IoFF ratio of 2.87 × 10^9 A/μm with/ON as 11.87 × 10^-4 A/μm and transconductance of 1.06× 10^-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.
