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Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor
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作者 菅洪彦 唐珏 +2 位作者 唐长文 何捷 闵昊 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第7期1328-1333,共6页
Dual pn junctions in lateral and vertical directions are formed by diffusing the p^+ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the s... Dual pn junctions in lateral and vertical directions are formed by diffusing the p^+ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^+-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor. 展开更多
关键词 on-chip inductor patterned dual pnjunctions eddy current substrate loss
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