Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate...Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.展开更多
With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silv...With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silvaco TCAD Tool so as to observe various electrical parameters at this gate length. The parameters under investigation are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL) by varying channel doping concentration, drain and source doping concentration and gate oxide thickness.展开更多
High performance pentacene organic thin film transistors （OTFT） were designed and fabricated using SiO2 deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass...High performance pentacene organic thin film transistors （OTFT） were designed and fabricated using SiO2 deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S-D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage VTH was -2.75±0.1V in 0-50V range, and that subthreshold slopes were 0.42±0.05V/dec. The field-effect mobility （μEF） of OTFT device increased with the increase of VDS, but the μEF of OTFT device increased and then decreased with increased VGS when VDS was kept constant. When VDS was -50V, on/off current ratio was 0.48×10^5 and subthreshold slope was 0.44V/dec. The μEF was 1.10cm^2/（V.s）, threshold voltage was -2.71V for the OTFT device.展开更多
Atomistic quantum simulation is performed to compare the performance of zero-Schottky-barrier and doped source-drain contacts carbon nanotube field effect transistors(CNTFETs) with strain applied. The doped source-dra...Atomistic quantum simulation is performed to compare the performance of zero-Schottky-barrier and doped source-drain contacts carbon nanotube field effect transistors(CNTFETs) with strain applied. The doped source-drain contact CNTFETs outperform the Schottky contact devices with and without strain applied. The off-state current in both types of contact is similar with and without strain applied. This is because both types of contact offer very similar potential barrier in off-state. However, the on-state current in doped contact devices is much higher due to better modulation of on-state potential profile, and its variation with strain is sensitive to the device contact type. The on/off current ratio and the inverse subthreshold slope are better with doped source-drain contact, and their variations with strain are relatively less sensitive to the device contact type. The channel transconductance and device switching performance are much better with doped source-drain contact, and their variations with strain are sensitive to device contact type.展开更多
The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents...The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.展开更多
The growing demand for high-performance logic transistors has driven the exponential rise in chip integration,while the transistors have been rapidly scaling down to sub-10 nm.The increasing leakage current and subthr...The growing demand for high-performance logic transistors has driven the exponential rise in chip integration,while the transistors have been rapidly scaling down to sub-10 nm.The increasing leakage current and subthreshold slope(SS) induced by short channel effect(SCE) result in extra heat dissipation during device operation.The performance of electronic devices based on two-dimensional(2D) semiconductors such as the transition metal dichalcogenides(TMDC) can significantly reduce power consumption,benefiting from atomically thin thickness.Here,we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors(MOSFETs) and 2D negative capacitance field effect transistors(NCFETs),outlining their potential in low-power applications as a technological option beyond scaled logic switches.Above all,we show our perspective at 2D low-power logic transistors,including the ultra-thin equivalent oxide thickness(EOT),reducing density of interface trap,reliability,operation speed etc.of 2D MOSFETs and NCFETs.展开更多
For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute devic...For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.展开更多
We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain ...We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.展开更多
For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel fi...For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.展开更多
A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs.Different short channel field effects,such as fringing fields,junction-induced lateral fields and ...A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs.Different short channel field effects,such as fringing fields,junction-induced lateral fields and substrate fields,are carefully investigated,and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model.Through analytical model-based simulation,the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations.Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model.The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET.The short channel effects are found to be reduced in an SON,thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope.This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.展开更多
A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFE...A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） region.It is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.展开更多
文摘Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.
文摘With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silvaco TCAD Tool so as to observe various electrical parameters at this gate length. The parameters under investigation are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL) by varying channel doping concentration, drain and source doping concentration and gate oxide thickness.
基金supported by the National Natural Science Foundation of China (Grant No 60576016)the National High Technology Research and Development Program of China (Grant No 2006AA03Z0412)+3 种基金the Beijing Natural Science Foundation of China (Grant No 2073030)the National Grand Fundamental Research 973 Program of China (Grant No 2003CB314707)the National Natural Science Foundation of China (Grant No 10434030)the Excellent Doctor's Science and Technology Innovation Foundation of Beijing Jiaotong University of China (Grant No 48024)
文摘High performance pentacene organic thin film transistors （OTFT） were designed and fabricated using SiO2 deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S-D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage VTH was -2.75±0.1V in 0-50V range, and that subthreshold slopes were 0.42±0.05V/dec. The field-effect mobility （μEF） of OTFT device increased with the increase of VDS, but the μEF of OTFT device increased and then decreased with increased VGS when VDS was kept constant. When VDS was -50V, on/off current ratio was 0.48×10^5 and subthreshold slope was 0.44V/dec. The μEF was 1.10cm^2/（V.s）, threshold voltage was -2.71V for the OTFT device.
文摘Atomistic quantum simulation is performed to compare the performance of zero-Schottky-barrier and doped source-drain contacts carbon nanotube field effect transistors(CNTFETs) with strain applied. The doped source-drain contact CNTFETs outperform the Schottky contact devices with and without strain applied. The off-state current in both types of contact is similar with and without strain applied. This is because both types of contact offer very similar potential barrier in off-state. However, the on-state current in doped contact devices is much higher due to better modulation of on-state potential profile, and its variation with strain is sensitive to the device contact type. The on/off current ratio and the inverse subthreshold slope are better with doped source-drain contact, and their variations with strain are relatively less sensitive to the device contact type. The channel transconductance and device switching performance are much better with doped source-drain contact, and their variations with strain are sensitive to device contact type.
基金Projects(61574109,61204092)supported by the National Natural Science Foundation of China
文摘The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.
文摘The growing demand for high-performance logic transistors has driven the exponential rise in chip integration,while the transistors have been rapidly scaling down to sub-10 nm.The increasing leakage current and subthreshold slope(SS) induced by short channel effect(SCE) result in extra heat dissipation during device operation.The performance of electronic devices based on two-dimensional(2D) semiconductors such as the transition metal dichalcogenides(TMDC) can significantly reduce power consumption,benefiting from atomically thin thickness.Here,we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors(MOSFETs) and 2D negative capacitance field effect transistors(NCFETs),outlining their potential in low-power applications as a technological option beyond scaled logic switches.Above all,we show our perspective at 2D low-power logic transistors,including the ultra-thin equivalent oxide thickness(EOT),reducing density of interface trap,reliability,operation speed etc.of 2D MOSFETs and NCFETs.
文摘For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.
文摘We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.
文摘For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.
文摘A generalized threshold voltage model based on two-dimensional Poisson analysis has been developed for SOI/SON MOSFETs.Different short channel field effects,such as fringing fields,junction-induced lateral fields and substrate fields,are carefully investigated,and the related drain-induced barrier-lowering effects are incorporated in the analytical threshold voltage model.Through analytical model-based simulation,the threshold voltage roll-off and subthreshold slope for both structures are compared for different operational and structural parameter variations.Results of analytical simulation are compared with the results of the ATLAS 2D physics-based simulator for verification of the analytical model.The performance of an SON MOSFET is found to be significantly different from a conventional SOI MOSFET.The short channel effects are found to be reduced in an SON,thereby resulting in a lower threshold voltage roll-off and a smaller subthreshold slope.This type of analysis is quite useful to figure out the performance improvement of SON over SOI structures for next generation short channel MOS devices.
文摘A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D（source/drain） region.It is found that an optimal source/drain-to-gate non-overlapped and high-A：spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering（DIBL） characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.
