In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combina...In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combination annealing,and chemical solution etching.The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm.After finishing the fabrication of devices,we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch.A poly-Si/SiGe core-shell JAMFETs was successfully demonstrated and it also exhibits a superior subthreshold swing of 81mV/dec and high on/off ratio>10^5 when annealing for 1hr at 600℃.The thermal diffusion process condition for this study are 1hr at 600℃ and 6hr at 700℃ for comparison.The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other.Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film.Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e.at higher temperature.This new process can still fabricate a comparable performance to classical planar FinFET in driving current.展开更多
The growing demand for high-performance logic transistors has driven the exponential rise in chip integration,while the transistors have been rapidly scaling down to sub-10 nm.The increasing leakage current and subthr...The growing demand for high-performance logic transistors has driven the exponential rise in chip integration,while the transistors have been rapidly scaling down to sub-10 nm.The increasing leakage current and subthreshold slope(SS) induced by short channel effect(SCE) result in extra heat dissipation during device operation.The performance of electronic devices based on two-dimensional(2D) semiconductors such as the transition metal dichalcogenides(TMDC) can significantly reduce power consumption,benefiting from atomically thin thickness.Here,we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors(MOSFETs) and 2D negative capacitance field effect transistors(NCFETs),outlining their potential in low-power applications as a technological option beyond scaled logic switches.Above all,we show our perspective at 2D low-power logic transistors,including the ultra-thin equivalent oxide thickness(EOT),reducing density of interface trap,reliability,operation speed etc.of 2D MOSFETs and NCFETs.展开更多
High performance pentacene organic thin film transistors （OTFT） were designed and fabricated using SiO2 deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass...High performance pentacene organic thin film transistors （OTFT） were designed and fabricated using SiO2 deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S-D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage VTH was -2.75±0.1V in 0-50V range, and that subthreshold slopes were 0.42±0.05V/dec. The field-effect mobility （μEF） of OTFT device increased with the increase of VDS, but the μEF of OTFT device increased and then decreased with increased VGS when VDS was kept constant. When VDS was -50V, on/off current ratio was 0.48×10^5 and subthreshold slope was 0.44V/dec. The μEF was 1.10cm^2/（V.s）, threshold voltage was -2.71V for the OTFT device.展开更多
Atomistic quantum simulation is performed to compare the performance of zero-Schottky-barrier and doped source-drain contacts carbon nanotube field effect transistors(CNTFETs) with strain applied. The doped source-dra...Atomistic quantum simulation is performed to compare the performance of zero-Schottky-barrier and doped source-drain contacts carbon nanotube field effect transistors(CNTFETs) with strain applied. The doped source-drain contact CNTFETs outperform the Schottky contact devices with and without strain applied. The off-state current in both types of contact is similar with and without strain applied. This is because both types of contact offer very similar potential barrier in off-state. However, the on-state current in doped contact devices is much higher due to better modulation of on-state potential profile, and its variation with strain is sensitive to the device contact type. The on/off current ratio and the inverse subthreshold slope are better with doped source-drain contact, and their variations with strain are relatively less sensitive to the device contact type. The channel transconductance and device switching performance are much better with doped source-drain contact, and their variations with strain are sensitive to device contact type.展开更多
The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents...The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.展开更多
With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silv...With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silvaco TCAD Tool so as to observe various electrical parameters at this gate length. The parameters under investigation are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL) by varying channel doping concentration, drain and source doping concentration and gate oxide thickness.展开更多
文摘In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combination annealing,and chemical solution etching.The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm.After finishing the fabrication of devices,we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch.A poly-Si/SiGe core-shell JAMFETs was successfully demonstrated and it also exhibits a superior subthreshold swing of 81mV/dec and high on/off ratio>10^5 when annealing for 1hr at 600℃.The thermal diffusion process condition for this study are 1hr at 600℃ and 6hr at 700℃ for comparison.The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other.Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film.Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e.at higher temperature.This new process can still fabricate a comparable performance to classical planar FinFET in driving current.
文摘The growing demand for high-performance logic transistors has driven the exponential rise in chip integration,while the transistors have been rapidly scaling down to sub-10 nm.The increasing leakage current and subthreshold slope(SS) induced by short channel effect(SCE) result in extra heat dissipation during device operation.The performance of electronic devices based on two-dimensional(2D) semiconductors such as the transition metal dichalcogenides(TMDC) can significantly reduce power consumption,benefiting from atomically thin thickness.Here,we discuss the progress of dielectric integration of 2D metal–oxide–semiconductor field effect transistors(MOSFETs) and 2D negative capacitance field effect transistors(NCFETs),outlining their potential in low-power applications as a technological option beyond scaled logic switches.Above all,we show our perspective at 2D low-power logic transistors,including the ultra-thin equivalent oxide thickness(EOT),reducing density of interface trap,reliability,operation speed etc.of 2D MOSFETs and NCFETs.
基金supported by the National Natural Science Foundation of China (Grant No 60576016)the National High Technology Research and Development Program of China (Grant No 2006AA03Z0412)+3 种基金the Beijing Natural Science Foundation of China (Grant No 2073030)the National Grand Fundamental Research 973 Program of China (Grant No 2003CB314707)the National Natural Science Foundation of China (Grant No 10434030)the Excellent Doctor's Science and Technology Innovation Foundation of Beijing Jiaotong University of China (Grant No 48024)
文摘High performance pentacene organic thin film transistors （OTFT） were designed and fabricated using SiO2 deposited by electron beam evaporation as gate dielectric material. Pentacene thin films were prepared on glass substrate with S-D electrode pattern made from ITO by means of thermal evaporation through self-organized process. The threshold voltage VTH was -2.75±0.1V in 0-50V range, and that subthreshold slopes were 0.42±0.05V/dec. The field-effect mobility （μEF） of OTFT device increased with the increase of VDS, but the μEF of OTFT device increased and then decreased with increased VGS when VDS was kept constant. When VDS was -50V, on/off current ratio was 0.48×10^5 and subthreshold slope was 0.44V/dec. The μEF was 1.10cm^2/（V.s）, threshold voltage was -2.71V for the OTFT device.
文摘Atomistic quantum simulation is performed to compare the performance of zero-Schottky-barrier and doped source-drain contacts carbon nanotube field effect transistors(CNTFETs) with strain applied. The doped source-drain contact CNTFETs outperform the Schottky contact devices with and without strain applied. The off-state current in both types of contact is similar with and without strain applied. This is because both types of contact offer very similar potential barrier in off-state. However, the on-state current in doped contact devices is much higher due to better modulation of on-state potential profile, and its variation with strain is sensitive to the device contact type. The on/off current ratio and the inverse subthreshold slope are better with doped source-drain contact, and their variations with strain are relatively less sensitive to the device contact type. The channel transconductance and device switching performance are much better with doped source-drain contact, and their variations with strain are sensitive to device contact type.
基金Projects(61574109,61204092)supported by the National Natural Science Foundation of China
文摘The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.
文摘With the need to improvement of speed of operation and the demand of low power MOSFET size scales down, in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silvaco TCAD Tool so as to observe various electrical parameters at this gate length. The parameters under investigation are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL) by varying channel doping concentration, drain and source doping concentration and gate oxide thickness.
