设计了一种基于加窗逐次逼近寄存器(WSAR)模拟数字转换器(ADC)的降压型DC-DC控制器,这种WSARADC适用于数字电源系统,通过对输入电压进行加窗处理,能有效地降低芯片的复杂度;并利用蚁群算法,对该DC-DC控制器的比例积分微分(PID)参数进行...设计了一种基于加窗逐次逼近寄存器(WSAR)模拟数字转换器(ADC)的降压型DC-DC控制器,这种WSARADC适用于数字电源系统,通过对输入电压进行加窗处理,能有效地降低芯片的复杂度;并利用蚁群算法,对该DC-DC控制器的比例积分微分(PID)参数进行了整定,使得整个系统能够稳定工作。电路使用BCD(Bipolar/CMOS/DMOS)0.5μm工艺,输入电压3.3 V,输出电压1 V,设计最大负载电流2 A,纹波小于9 m V,开关频率500 k Hz。经过验证,该降压型DC-DC控制器能满足数字电源的采样需求。展开更多
When the voltage of an analog input signal is equal to the supply voltage, it is difficult for a conventional successive approximation ADC to correctly convert the analog signal into digital signal. This paper introdu...When the voltage of an analog input signal is equal to the supply voltage, it is difficult for a conventional successive approximation ADC to correctly convert the analog signal into digital signal. This paper introduces an improved successive approximation ADC, which can convert the rail-to-rail input range and reduce sampling time through a track-and-hold circuit. Comparator offset cancellation and capacitor self-calibration techniques are used in this ADC. Measurement results show that the peak SNDR of this ADC reaches 72 dB and the signal effective bandwidth is up to 1.25 MHz. It consumes 1 mW in the test, and the figure of merit is 123 fJ/conversion-step.展开更多
针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm ...A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm CMOS. The charge redistribution （CR） design and an extra A E modulator for capacitance measurement are em- ployed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2. 1 mW.展开更多
为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提...为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。展开更多
文摘设计了一种基于加窗逐次逼近寄存器(WSAR)模拟数字转换器(ADC)的降压型DC-DC控制器,这种WSARADC适用于数字电源系统,通过对输入电压进行加窗处理,能有效地降低芯片的复杂度;并利用蚁群算法,对该DC-DC控制器的比例积分微分(PID)参数进行了整定,使得整个系统能够稳定工作。电路使用BCD(Bipolar/CMOS/DMOS)0.5μm工艺,输入电压3.3 V,输出电压1 V,设计最大负载电流2 A,纹波小于9 m V,开关频率500 k Hz。经过验证,该降压型DC-DC控制器能满足数字电源的采样需求。
文摘When the voltage of an analog input signal is equal to the supply voltage, it is difficult for a conventional successive approximation ADC to correctly convert the analog signal into digital signal. This paper introduces an improved successive approximation ADC, which can convert the rail-to-rail input range and reduce sampling time through a track-and-hold circuit. Comparator offset cancellation and capacitor self-calibration techniques are used in this ADC. Measurement results show that the peak SNDR of this ADC reaches 72 dB and the signal effective bandwidth is up to 1.25 MHz. It consumes 1 mW in the test, and the figure of merit is 123 fJ/conversion-step.
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
文摘A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm CMOS. The charge redistribution （CR） design and an extra A E modulator for capacitance measurement are em- ployed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2. 1 mW.
文摘为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。
