A low power 8-bit successive approximation register A/D for a wireless body sensor node

A power efficient 8-bit successive approximation register（SAR） A/D for the vital sign monitoring of a wireless body sensor network（WBSN） is presented.A charge redistribution architecture is employed.The prototype A/D is fabricated in 0.18μm CMOS.The A/D achieves 7.5ENOB with sampling rate varying from 64 kHz to 1.5 MHz. The power consumption varies from 10.8 to 225.7μW.

A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm CMOS. The charge redistribution （CR） design and an extra A E modulator for capacitance measurement are em- ployed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2. 1 mW.

An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.

Design of digital calibration based on variable step size of sub-binary SAR ADC

Addressing the impact of capacitor mismatch on the conversion accuracy of successive approximation register analog-to-digital converter(SAR ADC),a 12-bit 1 MS/s sub-binary SAR ADC designed using variable step size digital calibration was proposed.The least mean square(LMS)calibration algorithm was employed with a ramp signal used as the calibration input.Weight errors,extracted under injected disturbances,underwent iterative training to optimize weight values.To address the trade-off between conversion accuracy and speed caused by a fixed step size,a novel variable step size algorithm tailored for SAR ADC calibration was proposed.The core circuit and layout of the SAR ADC were implemented using the Taiwan Semiconductor Manufacturing Company(TSMC)0.35μm complementary metal-oxide-semiconductor(CMOS)commercial process.Simulation of the SAR ADC calibration algorithm was conducted using Simulink,demonstrating quick convergence and meeting conversion accuracy requirements compared to fixed step size simulation.The results indicated that the convergence speed of the LMS digital calibration algorithm with variable step size was approximately eight times faster than that with a fixed step size,also yielding a lower mean square error(MSE).After calibration,the simulation results for the SAR ADC exhibited an effective number of bit(ENOB)of 11.79 bit and a signal-to-noise and distortion ratio(SNDR)of 72.72 dB,signifying a notable enhancement in the SAR ADC performance.

A cryogenic SAR ADC for infrared readout circuits

comparatorAbstract： A cryogenic successive approximation register （SAR） analog to digital converter （ADC） is presented. It has been designed to operate in cryogenic infrared readout systems as they are cooled from room temperature to their final cryogenic operation temperature. In order to preserve the circuit＇s performance over this wide temperature range, a temperature-compensated time-based comparator architecture is used in the ADC, which provides a steady performance with ultra low power for extreme temperature （from room temperature down to 77 K） operation. The converter implemented in a standard 0.35 μm CMOS process exhibits 0.64 LSB maximum differential nonlinearity （DNL） and 0.59 LSB maximum integral nonlinearity （1NL）. It achieves 9.3 bit effective number of bits （ENOB） with 200 kS/s sampling rate at 77 K, dissipating 0.23 mW under 3.3 V supply voltage and occupies 0.8 × 0.3 mm^2.

A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

This paper presents a 12-bit column-parallel successive approximation register analog-to-digital con- verter （SAR ADC） for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital- to-analog converter （CDAC） and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-W supply and decreases linearly as the frame rate decreases.

A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator

A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

A single-ended 10-bit 200 kS/s 607 μ W SAR ADC with an auto-zeroing offset cancellation technique

Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows expo- nentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607/μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and- distortion ratio （SNDR） is 60.1 dB and the spurious-free dynamic range （SFDR） is 68.1 dB. The measured DNL is ±0.37/-0.06 LSB and INL is ±0.58/-0.22 LSB.

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measure- ment in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer （TIQ）-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capaci- tance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.

An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB

This paper presents a differential successive approximation register analog-to-digital converter（SAR ADC） with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout.The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.

An energy-efficient and highly linear switching capacitor procedure for SAR ADCs

An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VcM-based switching scheme. Moreover, the proposed method shows better linearity than the VcM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion- step. The measured peak DNL and 1NL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL 1 is observed at 4^-1 VFS and 4^-3 VFS, the same as the static nonlinearity model.

A single channel,6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC

This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter （SAR ADC） for ultrawide bandwidth （UWB） communication, prototyped in a SMIC 65-nm process. Based on the 3 bits/stage structure, resistive DAC, and the modified asynchronous successive approximation register control logic, the proposed ADC attains a peak spurious-free dynamic range （SFDR） of 41.95 dB, and a signal-to-noise and distortion ratio （SNDR） of 28.52 dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with a 40.71-dB SFDR and 30.02-dB SNDR. A four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03 mW, corresponding to a figure of merit of 189.17 fJ/step at 410 MS/s.

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

A 10-bit 50-MS/s reference-free low power successive approximation register （SAR） analog-to-digital converter （ADC） is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC （CDAC） is implemented to cancel the offset of the latch-type sense amplifier （SA） to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit （FOM） of 61.1 fJ/conversion-step.

Modeling of channel mismatch in time-interleaved SAR ADC

In a time-interleaved analog-to-digital converter （TI ADC）, several individual ADCs operate in parallel to achieve a higher sampling rate. Low power consumption as well as good linearity can be obtained by applying successive approximation register （SAR） converters as sub-channel ADCs. In spite of the advantages, this structure suffers from three mismatches, which are offset mismatch, gain mismatch, and time skew. This paper focuses on a TI SAR ADC with a number of channels. The mismatch effects in the frequency domain are analyzed and the derived close form formulas are verified based on Matlab. In addition, we clarify that the standard deviation of DNL and INL of an M-channel TI ADC is reduced by a factor of ~ compared to a single channel ADC. The formulas can be used to derive the corresponding requirements when designing a TI ADC. Our analysis process is able to inform the study of calibration algorithms.

A single channel, 6-bit 230-MS/s asynchronous SAR ADC based on 2 bits/stage

This paper proposes a single channel, 6-bit 230-MS/s asynchronous successive approximation register analog-to-digital converter （ADC） in an SMIC 65 nm CMOS technology. Through adopting the modified 2 bits/stage asynchronous control logic, the presented ADC actualizes a peak 40.90-dB spurious-free dynamic range and 29.05-dB signal-to-noise and distortion ratio at 230-MS/s sampling rate. Utilizing the dynamic comparator without the preamplifier, this work attains low-power design with only 0.93 mW power consumption and accomplishes a figure of merit of 174.67 fJ/step at 1 V supply voltage.

An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure （6 MSB 5 LSB） composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 #m 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 U/conversion-step.

A 12-bit 80 MS/s 2 mW SAR ADC with Deliberated Digital Calibration and Redundancy Schemes for Medical Imaging

In this article,we presented a 12-bit 80 MS/s low power successive approximation register(SAR)analog to digital converter(ADC)design.A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency.A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit.The prototype SAR ADC can work up to a sampling rate of 80 MS/s with the performance of>10.5 bit equivalent number of bits(ENOB),<±1 least significant bit(LSB)differential nonlinearity(DNL)&integrated nonlinearity(INL),while only consuming less than 2 mA current from a 1.1 V power supply.The calculated figure of merit(FoM)is 17.4 fJ/conversion-step.This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.

An 11-bit ENOB,accuracy-programmable,and non-calibrating time-mode SAR ADC

A 10 or 12 bit programmable successive approximation register（SAR） ADC incorporating improved time-domain comparator for bridge stress monitoring systems is presented.Techniques for improving the accuracy of time-domain comparator are presented.The application of these approaches is illustrated using results from an experimental 10 or 12 bit programmable SAR ADC.Prototyped in a 0.18-m,6M1P CMOS process,the ADC,at 12 bit,100 kS/s,achieves a Nyquist signal-to-noise-plus-distortion ratio（SNDR） of 68 dB（11 ENOB）,a spurious free dynamic range（SFDR） of 77.48 dB,while dissipating 558 W from a 1.8-V supply.Its differential nonlinearity（DNL） and integral nonlinearity（INL） are 0.2/-0.74 LSB and C1.27/-0.97 LSB,respectively.

A 10-bit 110 MHz SAR ADC with asynchronous trimming in 65-nm CMOS

A 10-bit 110 MHz SAR ADC with asynchronous trimming is presented.In this paper,a high linearity sampling switch is used to produce a constant parasitical barrier capacitance which would not change with the range of input signals.As a result,the linearity of the SAR ADC will increase with high linearity sampled signals.Farther more,a high-speed and low-power dynamic comparator is proposed which would reduce the comparison time and save power consumption at the same time compared to existing technology.Additionally,the proposed comparator provides a better performance with the decreasing of power supply.Moreover,a highspeed successive approximation register is exhibited to speed up the conversion time and will reduce about 50%register delay.Lastly,an asynchronous trimming method is provided to make the capacitive-D AC settle up completely instead of using the redundant cycle which would prolong the whole conversion period.This SAR ADC is implemented in 65-nm CMOS technology the core occupies an active area of only 0.025 mm-2 and consumes 1.8 mW.The SAR ADC achieves SFDR 〉 68 dB and SNDR 〉 57 dB,resulting in the FOM of 28 f J/conversion-step.From the test results,the presented SAR ADC provides a better FOM compared to previous research and is suitable for a kind of ADC IP in the design SOC.

A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS

This paper presents a 10-bit 80-MS/s successive approximation register（SAR） analog-to-digital converter （ADC） suitable for integration in a system on a chip（SoC）.By using the top-plate-sample switching scheme and a split capacitive array structure,the total capacitance is dramatically reduced which leads to low power and high speed.Since the split structure makes the capacitive array highly sensitive to parasitic capacitance,a three-row layout method is applied to the layout design.To overcome the charge leakage in the nanometer process,a special input stage is proposed in the comparator.As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock,and a tunable clock generator is implemented.The prototype was fabricated in 65 nm 1P9M （one-poly-nine-metal） GP（general purpose） CMOS technology.Measurement results show a peak signal-to-noise and distortion ratio（SINAD） of 48.3 dB and 1.6 mW total power consumption with a figure of merit（FOM） of 94.8 fJ/conversion-step.