Electromagnetic Performance Analysis of Variable Flux Memory Machines with Series-magnetic-circuit and Different Rotor Topologies

In this paper,the electromagnetic performance of variable flux memory(VFM)machines with series-magnetic-circuit is investigated and compared for different rotor topologies.Based on a V-type VFM machine,five topologies with different interior permanent magnet(IPM)arrangements are evolved and optimized under same constrains.Based on two-dimensional(2-D)finite element(FE)method,their electromagnetic performance at magnetization and demagnetization states is evaluated.It reveals that the iron bridge and rotor lamination region between constant PM(CPM)and variable PM(VPM)play an important role in torque density and flux regulation(FR)capabilities.Besides,the global efficiency can be improved in VFM machines by adjusting magnetization state(MS)under different operating conditions.

20 MHz Switched-Current Sample-and-Hold Circuit with Low Charge Injection

A switched-current sample-and-hold circuit with low charge injection was proposed. To obtain low noise and charge injection, the zero-voltage switching was used to remove the signal-dependent charge injection, and the signal-independent charge injection was reduced by removing the feed-through voltage from the input port of the memory transistor directly. This current sample-and-hold circuit was implemented using CMOS 180 nm 1.8 V technology. For a 0.8 MHz sinusoidal signal input, the simulated signal-to-noise and distortion ratio and total harmonic distortion were improved from 53.74 dB and -51.24 dB to 56.53 dB and -54.36 dB at the sampling rate of 20 MHz respectively, with accuracy of 9.01 bit and power consumption of 0.44 mW.

SWITCHED-CURRENT FILTER DESIGN USING CASCADED SECTIONS

A new analogue sampled-data active device, named as a switched-current operationalamplifier (SIOA), is presented. The use of active circuit elements may simplify drawing the circuitdiagram significantly greatly and may permit easier analysis and synthesis of SI networks. Anumber of all pole and elliptic (second-or third-order) switched-current (SI) filters are derivedfrom the switched capacitor prototypes. These can be used as simple self-contained filters or asfilter sections in the cascaded realizations of a higher order transfer functions. To illustrate theapproach, a fifth-order low-pass filter is designed.

A NEW MULTIFUNCTION SWITCHED-CURRENT FILTER

A new switched-current(SI)biquadratic filter is presented which can simultaneouslyprovide the low-pass,high-pass and band-pass filters in a single building block.A symbol torepresent the universal SI integrator is also introduced.It can simplify the analysis and synthesisof SI networks.

Promotion of structural plasticity in area V2 of visual cortex prevents against object recognition memory deficits in aging and Alzheimer's disease rodents

Memory deficit,which is often associated with aging and many psychiatric,neurological,and neurodegenerative diseases,has been a challenging issue for treatment.Up till now,all potential drug candidates have failed to produce satisfa ctory effects.Therefore,in the search for a solution,we found that a treatment with the gene corresponding to the RGS14414protein in visual area V2,a brain area connected with brain circuits of the ventral stream and the medial temporal lobe,which is crucial for object recognition memory(ORM),can induce enhancement of ORM.In this study,we demonstrated that the same treatment with RGS14414in visual area V2,which is relatively unaffected in neurodegenerative diseases such as Alzheimer s disease,produced longlasting enhancement of ORM in young animals and prevent ORM deficits in rodent models of aging and Alzheimer’s disease.Furthermore,we found that the prevention of memory deficits was mediated through the upregulation of neuronal arbo rization and spine density,as well as an increase in brain-derived neurotrophic factor(BDNF).A knockdown of BDNF gene in RGS14414-treated aging rats and Alzheimer s disease model mice caused complete loss in the upregulation of neuronal structural plasticity and in the prevention of ORM deficits.These findings suggest that BDNF-mediated neuronal structural plasticity in area V2 is crucial in the prevention of memory deficits in RGS14414-treated rodent models of aging and Alzheimer’s disease.Therefore,our findings of RGS14414gene-mediated activation of neuronal circuits in visual area V2 have therapeutic relevance in the treatment of memory deficits.

Discrete-Time Chaotic Circuits for Implementation of Tent Map and Bernoulli Map

Discrete-time chaotic circuit implementations of a tent map and a Bernoulli map using switched-current （SI） techniques are presented. The two circuits can be constructed with 16 MOSFET＇s and 2 capacitors. The simulations and experiments built with commercially available IC＇s for the circuits have demonstrated the validity of the circuit designs. The experiment results also indicate that the proposed circuits are integrable by a standard CMOS technology. The implementations are useful for studies and applications of chaos.

Analysis and modeling of resistive switching mechanisms oriented to resistive random-access memory

With the progress of the semiconductor industry,the resistive random-access memory（RAM） has drawn increasing attention.The discovery of the memristor has brought much attention to this study.Research has focused on the resistive switching characteristics of different materials and the analysis of resistive switching mechanisms.We discuss the resistive switching mechanisms of different materials in this paper and analyze the differences of those mechanisms from the view point of circuitry to establish their respective circuit models.Finally,simulations are presented.We give the prospect of using different materials in resistive RAM on account of their resistive switching mechanisms,which are applied to explain their resistive switchings.

Model Design of Electrically Erasable EEPROM Memory Cell

This article introduces an EEPROM memory cell model that is different from the equivalent capacitance model. This model uses high-frequency components in circuit design, including MOS transistors, zener diodes, resistors, capacitors, etc., and builds a model that can be used in most analog environments. The simulation of the transient process of write and read operations helps designers understand the working principle of EEPROM, and it can also be applied to the overall circuit design. According to the structure and working principle of the EEPROM cell device, a model of its equivalent circuit is established, and the read, write, and erase operations of the EEPROM cell are transiently simulated using this model. The simulation results verify the correctness of the model.

Structural Design of an Electrically Erasable EEPROM Memory Cell

EEPROM is an electrically erasable and programmable memory. The technology is mature and stable with low cost, so it is the mainstream in the application of electronic products in daily life. People use it in every way. In the fields of personal identity card, bank card, medical insurance card, traffic card and other smart cards, which are closely related to personal property, and in the field of communication system and other consumer electronic products such as PDA and digital camera, EEPROM is used. In instruments and other embedded systems, such as smart flowmeters, it is usually necessary to store information such as setting parameters, field data, etc., which requires that the system is not lost when it is powered down so that the data you originally set could be restored next time. Therefore, a certain capacity of?EEPROM.?Through the storage or release of electrons on the floating gate tube of the memory cell, the memory appears to be on or off when the floating gate tube is read, so its logic value will be judged as “0”?Or?“1”. The definition of logic “0” or “1” varies depending on the logical design of the product. This work designs a memory cell consisting of two transistors. The NMOS tube is used as a selection tube and controlled by the word line. It can withstand a part of the high voltage and reduce the probability of breakdown of the ultra-thin oxide layer of the floating gate transistor. As a storage tube, the EEPROM device model designed in this paper can work well through the tunnel oxide layer to store data, achieving better storage functions, higher work efficiency, and lower power consumption.

基于最优独立通路的通风网络调节位置优化

独立通路在通风网络中具有重要的作用,寻找一种能够快速搜索复杂网络独立通路的算法具有重要意义。采用通路法进行网络调节可以优化通风网络的调节效果。传统的通路搜索算法搜索的通路一般较长,无法处理特殊网络的搜索问题且无法同时保证通路的独立性和完备性。为了解决传统通路搜索算法存在的问题,系统研究了独立通路搜索的关键技术,在分析传统通路搜索算法局限性的基础上,提出了1种改进的独立通路搜索算法。该算法处理了网络中的割边、割点问题,避免了算法陷入死循环或异常中断;结合BFS法改进了通路搜索的性能,便于控制通路中关键分支的搜索;分析独立通路完备性搜索失败的原因,并通过记忆搜索策略解决了含有单向回路的通路搜索问题。利用改进的独立通路搜索算法,提出了1种自适应通路调节法,该方法可以获得1棵具有最优调节位置的最佳通路调节树,从而得到一组最优增阻调节解。

基于d-q变换及WOA-LSTM的异步电机定子匝间短路故障诊断方法

为了实现对异步电机定子绕组匝间短路故障的可靠在线诊断,提出一种基于d-q变换及鲸鱼优化算法(WOA)优化的长短期记忆网络(LSTM)的故障诊断方法。通过理论推导可知,d-q变换可有效提取定子电流中的特征频谱数据。采用鲸鱼优化算法对长短期记忆网络中的3个关键参数进行优化,建立WOA-LSTM故障分类模型。为了验证基于d-q变换和WOA-LSTM故障诊断方法的有效性,分别以小波变换、快速傅里叶变换及d-q变换提取电流频谱数据作为输入数据集,以一台YE2-100L1-4型异步电机为实验对象进行实验验证。研究结果表明:相比于小波变换及快速傅里叶变换,采用d-q变换能更准确的提取出定子电流中的故障特征,更精确地反映电机故障状态,有助于提高故障分类准确率;相比于传统的LSTM算法,经WOA优化后的LSTM算法分类准确率可达98.3%,能可靠地实现不同程度匝间短路故障的诊断。

鲸鱼优化算法-双向长短期记忆神经网络用于断路器机械剩余寿命的预测研究

低压断路器的安全可靠是电力系统能否稳定运行的关键一环,因此对断路器进行退化趋势预测和剩余寿命评估具有重要意义。基于鲸鱼优化算法(whale optimization algorithm,WOA)和双向长短期记忆神经网络(bidirectional long short-term memory,BiLSTM)提出了一种断路器操动机构剩余寿命的预测方法,首先采用Pearson相关系数法对获得的原始监测数据进行筛选,选择与断路器开断次数相关度较高的数据作为关键退化特征量,基于主成分分析法进行数据融合获得能够综合表征断路器运行状态的健康指数;随后使用滑动时间窗的方法对健康指数时间序列进行重构,再通过WOA-Bi LSTM寻优获得的最佳模型对健康指数进行时间序列预测,从而获得断路器未来多步的退化趋势;最后再根据设定的失效阈值,确定断路器操动机构的剩余寿命。实例验证表明,该文提出的混合预测模型预测精度最高可达96.43%,相比于其他传统预测模型显著提高,对于断路器的实际运维工作具有一定的指导意义。

NiMnGa磁控形状记忆合金纵振式换能器

为实现低频、小尺寸水下声源,利用具有大应变、快速响应和高能量密度等优势的NiMnGa合金为驱动元件设计了水声换能器。基于NiMnGa合金变形原理,建立了NiMnGa纵振式换能器物理模型,推导了等效电路。通过有限元法,实现了NiMnGa纵振式换能器电磁-机械-声的多物理场耦合仿真,用于预测换能器的水下声学性能。制作了小型NiMnGa纵振式换能器样机,并在水中测试了500~800 Hz频带内的声源级。实验结果表明,换能器样机辐射面直径为8 mm,水中谐振频率为700 Hz,最大声源级为115.5 dB。

考虑不同个性特征的忆阻记忆电路

提出了一种考虑不同个性特征的忆阻记忆电路,该电路由感知模块、情感生成模块和记忆突触模块组成。为了正确模拟生物神经元从感知刺激到响应的过程,在感知模块中采用易失性忆阻器来构建感知神经元。情感生成模块利用阈值型忆阻器作为情感突触,实现了不同人格到情绪的转换。记忆突触模块则整合情绪信号和学习信号,利用忆阻突触的可塑性实现学习和遗忘的功能。PSPICE仿真结果表明,所提出电路能正确模拟不同个性特征对记忆的影响。

基于改进Bi-LSTM的虚回路自动校验方法研究

针对智能变电站中虚回路人工校验效率低下、依赖于变电站配置描述(Substation configuration description,SCD)文件中虚端子定义不规范等问题,提出一种基于改进双向长短时记忆网络(Bi-directional long short-term memory,Bi-LSTM)的虚回路自动校验方法。首先,利用Word2vec模型对虚端子描述文本进行向量化编码,解决了虚端子描述文本的非结构化问题,使其能够在后续处理中被有效识别和分析。然后,引入了注意力机制与Bi-LSTM网络相结合的方式,以更全面地提取虚端子描述文本的语义特征。通过对比非标准虚端子与标准虚端子之间的相似度,实现了非标准虚端子的智能匹配,并建立了一个标准虚端子库作为基础数据支持。接着,利用经过验证的SCD文件与标准虚端子库,构建了虚回路模板库,该模板库能够有效存储并管理各类智能变电站设备的虚回路信息。最终,基于虚回路模板库实现了虚回路的自动校验,显著提升了虚回路校验过程的效率和准确性。试验结果表明,所提方法不仅提升了智能变电站虚回路校验的自适应性和精确度,还能够有效降低人工校验的工作量,显著提高智能变电站的自动化运行水平。该研究为未来智能变电站的虚回路校验和管理提供了重要的技术参考。

基于共享总线结构的存储器内建自测试电路

随着片上系统处理的数据增多,数据存储器测试逻辑相应增加,在保证测试功能的同时减小测试电路面积是当下急需解决的问题。基于共享总线结构的存储器内建自测试(MBIST)电路,通过将多个存储器引脚信号进行复用的方式,对存储器进行层次化设计,将物理存储器拼接组成逻辑存储器模块,再整合多个逻辑存储器成为一个大的存储器集模块,MBIST控制器针对存储器集进行MBIST,从而减少测试逻辑数量以达到减小测试电路占用面积的目的。通过实验证明,该结构可以满足MBIST相关需求,相较于针对单颗存储器测试的传统MBIST电路面积减小了21.44%。该方案具有良好的实用性,可以为相关存储器测试设计提供参考。

面向存算架构的神经网络数字系统设计

随着深度学习与神经网络的不断发展,庞大的计算量使得传统的冯·诺依曼架构设备面临“存储墙”等问题,因此“存内计算(Compute-In-Memory,CIM)”成为满足神经网络高时效需求和高运算量要求的主流设计方向。针对高密度数据的高性能计算提供高速且节能的解决方案,设计了一款神经网络加速器。首先,完成了对ResNet14神经网络的量化,依据其结构设计了一种面向存内计算的数字系统。而后,为了增强该系统的多网络适配性,提出了一种兼容性架构构想,使该数字系统可适配ResNet18或其他卷积神经网络的部分卷积层。最后,将该系统加载到FPGA上进行验证。在10 MHz的时钟频率下,以Cifar-10和MNIST数据集进行目标分类任务,分别得到60 FPS下84.17%和98.79%的准确率,具有更小的数据位宽和相近的准确率。

Data-Driven Fault Detection of Multiple Open-Circuit Faults for MMC Systems Based on Long Short-Term Memory Networks

This paper presents a long short-term memory(LSTM)-based fault detection method to detect the multiple open-circuit switch faults of modular multilevel converter(MMC)systems with full-bridge sub-modules(FB-SMs).Eighteen sensor signals of grid voltages,grid currents and capacitance voltages of MMC for single and multi-switch faults are collected as sampling data.The output signal characteristics of four types of single switch faults of FB-SM,as well as double switch faults in the same and different phases of MMC,are analyzed under the conditions of load variations and control command changes.A multi-layer LSTM network is devised to deeply extract the fault characteristics of MMC under different faults and operation conditions,and a Softmax layer detects the fault types.Simulation results have confirmed that the proposed LSTM-based method has better detection performance compared with three other methods:K-nearest neighbor(KNN),naive bayes(NB)and recurrent neural network(RNN).In addition,it is highly robust to model uncertainties and Gaussian noise.The validity of the proposed method is further demonstrated by experiment studies conducted on a hardware-in-the-loop(HIL)testing platform.

船舶发电机定子绕组匝间短路故障预警

为保障船舶的安全航行,需要对船舶发电机定子绕组早期匝间短路故障进行预警。首先,通过同步发电机的数学模型对正常运行和不同程度的匝间短路故障进行仿真,选取负序电流分量和电磁转矩作为故障特征量并进行信息融合;然后,使用CNN-BiLSTM网络对特征量进行回归预测得到网络预测的残差;最后,根据残差的变化趋势和设定的阈值来判断故障的发展情况。结果表明,建立的模型可以实现定子绕组匝间短路故障的预警,并且基于自适应原理设置的动态阈值会比固定阈值提前确认故障。

SOT-MRAM读电路泄电结构优化

自旋轨道矩磁性随机存储器(SOT-MRAM)作为第四代磁随机存储器广受关注。SOT-MRAM为三端结构,应用于2T2R结构时,不对称写入容易导致电荷积累,从而对读产生影响,甚至导致读取错误的发生。因此研究针对SOT-MRAM特点的读电路泄电结构,减小写入对读取通路的影响具有重要意义。本文针对SOT-MRAM写入不对称导致电荷积累问题,对比了两种泄电电路结构,有效降低了首个读周期的读取时间延迟。研究了引入的泄电结构对位线电容的容忍度的影响。分析了位线电容差异导致读取不对称的机理,结合首个读周期读取时间延迟问题,提出了适合SOT-MRAM特点的读取电路泄电结构。本文的研究为SOT-MRAM读取电路的设计提供了新思路。