A General Method in the Synthesis of Ternary Double Pass-Transistor Circuits

A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.

Nonlinear Auto-Companding Method for Behavioral Modeling of Switched-Current Circuits

A wavelet collocation method with nonlinear auto companding is proposed for behavioral modeling of switched current circuits.The companding function is automatically constructed according to the initial error distribution obtained through approximating the input output function of the SI circuit by conventional wavelet collocation method.In practical applications,the proposed method is a general purpose approach,by which both the small signal effect and the large signal effect are modeled in a unified formulation to ease the process of modeling and simulation.Compared with the published modeling approaches,the proposed nonlinear auto companding method works more efficiently not only in controlling the error distribution but also in reducing the modeling errors.To demonstrate the promising features of the proposed method,several SI circuits are employed as examples to be modeled and simulated.

Fault diagnosis method for switch control circuit based on SVM-AdaBoost

In order to realize the fault diagnosis of the control circuit of all-electronic computer interlocking system(ACIS)for railway signals,taking a five-wire switch electronic control module as an research object,we propose a method of selecting the sample set of the basic classifier by roulette method and realizing fault diagnosis by using SVM-AdaBoost.The experimental results show that the proportion of basic classifier samples affects classification accuracy,which reaches the highest when the proportion is 85%.When selecting the sample set of basic classifier by roulette method,the fault diagnosis accuracy is generally higher than that of the maximum weight priority method.When the optimal proportion 85%is taken,the accuracy is highest up to 96.3%.More importantly,this way can better adapt to the critical data and improve the anti-interference ability of the algorithm,and therefore it provides a basis for fault diagnosis of ACIS.

Full Graph Methods of Switched Current Circuit Solution

Circuits with switched current are described by an admittance matrix and seeking current transfers then means calculating the ratio of algebraic supplements of this matrix. As there are also graph methods of circuit analysis in addition to algebraic methods, it is clearly possible in theory to carry out an analysis of the whole switched circuit in two-phase switching exclusively by the graph method as well. For this purpose it is possible to plot a Mason graph of a circuit, use transformation graphs to reduce Mason graphs for all the four phases of switching, and then plot a summary graph from the transformed graphs obtained this way. First the author draws nodes and possible branches, obtained by transformation graphs for transfers of EE （even-even） and OO （odd-odd） phases. In the next step, branches obtained by transformation graphs for EO and OE phase are drawn between these nodes, while their resulting transfer is 1 multiplied by z^1/2. This summary graph is extended by two branches from input node and to output node, the extended graph can then be interpreted by the Mason＇s relation to provide transparent current transfers. Therefore it is not necessary to compose a sum admittance matrix and to express this consequently in numbers, and so it is possible to reach the final result in a graphical way.

低压自动转换开关电器(ATSE)选择要点分析

通过对不同类型ATSE的结构特点、主体元件、技术参数(额定工作电压及使用类别、额定工作电流、额定限制短路电流、转换条件、返还条件、转换时间、主触头位置数、极数等)的对比分析,阐述在不同使用环境下ATSE的选择要点。

Address switching:Reforming the architecture and traffic of Internet

The success of the Internet is largely ascribable to the packet-switching scheme, which, however, also presents major challenges. Having identified three missing links in the current Internet architecture based on our long-term experiences of designing and operating large-scale backbones, we put forward a new, but incrementally deployable, network schemc address switching. The address switching has both the advantages of packet switching and circuit switching; it supplies the missing links in the current Internet architecture and can reform the Internet traffic. Our analysis, protocol design and ex- periments indicate that the address switching can greatly improve the quality of service （QoS）, security and routing scalability of today＇s Internet. So it can provide flexible, high-performance and ＂per-service＂ networking for the scientific research communities. Moreover, it can provide a fairer and more sustainable business model for the commodity Internet.

Scalable and Practical Nonblocking Switching Networks

Large-scale strictly nonblocking （SNB） and wide-sense nonblocking （WSNB） networks may be infeasible due to their high cost. In contrast, rearrangeable nonblocking （RNB） networks are more scalable because of their much lower cost. However, RNB networks are not suitable for circuit switching. In this paper, the concept of virtual nonblockingness is introduced. It is shown that a virtual nonblocking （VNB） network functions like an SNB or WSNB network, but it is constructed with the cost of an RNB network. The results indicate that for large-scale circuit switching applications, it is only needed to build VNB networks.

Testability Analysis at Switch Level for CMOS Circuits

In this paper we propose a controllability and observability measure at switch level for CMOS circuits based on the cost analysis approach.The complexity of the algorithm is nearly linear.

All-optical functions based on semiconductor ring lasers

Semiconductor ring laser （SRL） has been shown to possess robust bistability between its two possible directions, i.e., clockwise （cw） and counter-clockwise （ccw） lasing, routinely demonstrating directional extinction ratio （DER） of 〉 25 dB. In this paper, experimental schemes and results using the SRL as a universal photonic digital element to form all-optical logic, memory, and signal processing circuits are summarized. It is demonstrated that the SRL can be used for both combinatorial and sequential logic functions, and as all-optical regeneration devices. Furthermore, it is shown that a SRL logic circuit can be all-optically reconfigured to perform different all-optical logic functions.

Research on performance of multicasting in optical packet switched networks

Different multicasting schemes in optical packet switched networks are discussed, including the parallel mode, serial mode, and hybrid mode multicasting schemes. Simulated modeling technique is applied to compare the network-level performance of the three multicasting schemes. A conclusion can be drawn from the results that since the hybrid-mode multicasting scheme can increase the multicast success ratio and reduce the packet retransmission times compared with the other two schemes, it is the best choice for delivering multicasting sessions in the optical packet switched networks.

Analysis of IPACT network performance considering channel switch latency for WDM-EPON

In wavelength-division multiplexing （WDM） ethernet passive optical networks （EPONs）, to realize the statistical multiplexing of upstream wavelength resources, some optical tunable components are introduced in the optical network units. However, the switch latency （SL） of these tunable components constrains the performance of WDM-EPON. In this letter, we extend the mathematical model of the WDM interleaved polling with adaptive cycle time （IPACT） scheme by additionally considering the SL conditions. We also investigate the effect of channel SL on network performance. The simulation results show that the performance of WDM-IPACT-SL deteriorates as the SL increases.

Extending path computation element for lightpath restoration in wavelength-switched optical networks

Current generalized multi-protocol label switching （GMPLS） standards do not include adequate models for wavelength-switched optical networks （WSON） in recovery mechanisms. In this letter, GMPLS/path computation element （PCE） extensions are applied for the restoration of the lightpaths disrupted by collision or optical impairment. A reserved deflection routing scheme is proposed to achieve fast restoration. It uses the expanded PCE component to compute and assign the backup paths for lightpath recovery. Numerical results demonstrate that this scheme is effective and low cost.

Fault-Tolerant Tree-Based Multicasting in Mesh Multicomputers

We propose a fault-tolerant tree-based multicast algorithm for 2-dimensional (2-D) meshes based on the concept of the extended safety level which is a vector associated with each node to capture fault information in the neighborhood. In this approach each destination is reached through a minimum number of hops. In order to minimize the total number of traffic steps, three heuristic strategies are proposed. This approach can be easily implemented by pipelined circuit switching (PCS). A simulation study is conducted to measure the total number of traffic steps under different strategies. Our approach is the first attempt to address the fault- tolerant tree-based multicast problem in 2-D meshes based on limited global information with a simple model and succinct information.