This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the ...This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of dis- tributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to- noise plus distortion ratio （SNDR） is 32.13 dB and the spurious-free dynamic range （SFDR） is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.展开更多
An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared ...An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VcM-based switching scheme. Moreover, the proposed method shows better linearity than the VcM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion- step. The measured peak DNL and 1NL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL 1 is observed at 4^-1 VFS and 4^-3 VFS, the same as the static nonlinearity model.展开更多
基金Project supported by the National High-Tech Research and Development Program of China(No.2013 AA014101)the National Science and Technology Program of China(No.2012BAI13B07)
文摘This paper presents a 6-b successive approximation register （SAR） ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of dis- tributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to- noise plus distortion ratio （SNDR） is 32.13 dB and the spurious-free dynamic range （SFDR） is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.
基金Project supported by the National Natural Science Foundation of China(Nos.61234002,61322405,61306044,61376033)the National High-Tech Program of China(Nos.2012AA012302,2013AA014103)
文摘An energy-efficient and highly linear capacitor switching procedure for successive approximation regis- ter （SAR） ADCs is presented. The proposed switching procedure achieves 37% less switching energy when compared to the well-known VcM-based switching scheme. Moreover, the proposed method shows better linearity than the VcM-based one. The proposed switching procedure is applied to a 10-bit 1.0 V 300 kS/s SAR ADC implemented in 0.18μm standard CMOS. The measured results show the SAR ADC achieves an SNDR of 55.48 dB, SFDR of 66.98 dB, and consumes 2.13 μW at a 1.0 V power supply, resulting in a figure-of-merit of 14.66 fJ/conversion- step. The measured peak DNL and 1NL are 0.52/-0.47 LSB and 0.72/-0.79 LSB, respectively, and the peak INL 1 is observed at 4^-1 VFS and 4^-3 VFS, the same as the static nonlinearity model.
