New Synchronization Algorithm and Analysis of Its Convergence Rate for Clock Oscillators in Dynamical Network with Time-Delays

New synchronization algorithm and analysis of its convergence rate for clock oscillators in dynamical network with time-delays are presented.A network of nodes equipped with hardware clock oscillators with bounded drift is considered.Firstly,a dynamic synchronization algorithm based on consensus control strategy,namely fast averaging synchronization algorithm （FASA）,is presented to find the solutions to the synchronization problem.By FASA,each node computes the logical clock value based on its value of hardware clock and message exchange.The goal is to synchronize all the nodes＇ logical clocks as closely as possible.Secondly,the convergence rate of FASA is analyzed that proves it is related to the bound by a nondecreasing function of the uncertainty in message delay and network parameters.Then,FASA＇s convergence rate is proven by means of the robust optimal design.Meanwhile,several practical applications for FASA,especially the application to inverse global positioning system （IGPS） base station network are discussed.Finally,numerical simulation results demonstrate the correctness and efficiency of the proposed FASA.Compared FASA with traditional clock synchronization algorithms （CSAs）,the convergence rate of the proposed algorithm converges faster than that of the CSAs evidently.

Scalable Clock Synchronization Analysis:A Symmetric Noncooperative Output Feedback Tubes-MPC Approach

In the cyber-physical environment,the clock synchronization algorithm is required to have better expansion for network scale.In this paper,a new measurement model of observability under the equivalent transformation of minimum mean square error(MMSE)is constructed based on basic measurement unit(BMU),which can realize the scaled expansion of MMSE measurement.Based on the state updating equation of absolute clock and the decoupled measurement model of MMSElike equivalence,which is proposed to calculate the positive definite invariant set by using the theoretical-practical Luenberger observer as the synthetical observer,the local noncooperative optimal control problem is built,and the clock synchronization system driven by the ideal state of local clock can reach the exponential convergence for synchronization performance.Different from the problem of general linear system regulators,the state estimation error and state control error are analyzed in the established affine system based on the set-theoryin-control to achieve the quantification of state deviation caused by noise interference.Based on the BMU for isomorphic state map,the synchronization performance of clock states between multiple sets of representative nodes is evaluated,and the scale of evaluated system can be still expanded.After the synchronization is completed,the state of perturbation system remains in the maximum range of measurement accuracy,and the state of nominal system can be stabilized at the ideal state for local clock and realizes the exponential convergence of the clock synchronization system.

Heuristics Scheduling Algorithm on the Links Scheduling of Satellite-Ground Clock Synchronization and Ephemeris Uploading in COMPASS System

The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling goal and constraint character,a heuristics rule-based multi-stage link scheduling algorithm was put forward.The algorithm distinguishes the on-off-frontier satellites from the others and schedules them by turns.The paper presented the main flow as well as the detailed design of the rule.Finally based on the current COMPASS global system,some typical resources and constraints are selected to generate an instance.Then the comparison analysis between the heuristics scheduling algorithm and three other traditional scheduling strategies are carried out.The result shows the validity and reasonability of the multi-stage strategy.

Iterative quantum algorithm for distributed clock synchronization

Clock synchronization is a well-studied problem with many practical and scientific applications.We propose an arbitrary accuracy iterative quantum algorithm for distributed clock synchronization using only three qubits.The n bits of the time difference between two spatially separated clocks can be deterministically extracted by communicating only O（n） messages and executing the quantum iteration process n times based on the classical feedback and measurement operations.Finally,we also give the algorithm using only two qubits and discuss the success probability of the algorithm.

A scheme for implementing quantum clock synchronization algorithm in cavity QED

In this paper, we propose a scheme for implementing the quantum clock synchronization （QCS） algorithm in cavity quantum electrodynamic （QED） formalism. Our method is based on three-level lader-type atoms interacting with classical and quantized cavity fields. Atom-qubit realizations of three-qubit and four-qubit QCS algorithms are explicitly presented.

An Improved Kalman Filter Positioning Method in NLOS Environment

In the precision positioning system, NLOS(Non Line of Sight) propagation and clock synchronization error caused by multiple base stations are the main reasons for reducing the reliability of communication and positioning accuracy. So, in the NLOS environment, it has an important role to eliminate the clock synchronization problem in the positioning system. In order to solve this problem, this paper proposes an improved Kalman filter localization method NLOS-K(Non Line of Sight-Kalman filter). First, the maximum likelihood estimation algorithm is used to iterate. Then, the Kalman filter algorithm is implemented and the Kalman gain matrix is redefined. The clock drift is compensated so that the clock between the master and slave base stations remains synchronized. The experimental results show that in the non-lineof-sight environment, compared with other algorithms, the positioning accuracy error of the improved algorithm is about 5 cm, and the accuracy compared with other algorithms is 97%. In addition, the influence of bandwidth and spectral density on the method is analyzed, and the accuracy and stability of positioning are improved as a whole.

A new synchronization scheme based on time division multiplexing and wavelength division multiplexing technology for practical quantum key distribution system

Three clock synchronization schemes for a quantum key distribution system are compared experimentally through the outdoor fibre and the interaction physical model of the the clock signal and the the quantum signal in the quantum key distribution system is analysed to propose a new synchronization scheme based on time division multiplexing and wavelength division multiplexing technology to reduce quantum bits error rates under some transmission rate conditions, The proposed synchronization scheme can not only completely eliminate noise photons from the bright background light of the the clock signal, but also suppress the fibre nonlinear crosstalk.

A Survey on Clock Synchronization in the Industrial Internet

Clock synchronization is one of the most fundamental and crucial network communication strategies.With the expansion of the Industrial Internet in numerous industrial applications,a new requirement for the precision,security,complexity,and other features of the clock synchronization mechanism has emerged in various industrial situations.This paper presents a study of standardized clock synchronization protocols and techniques for various types of networks,and a discussion of how these protocols and techniques might be classified.Following that is a description of how certain clock synchronization protocols and technologies,such as PROFINET,Time-Sensitive Networking(TSN),and other well-known industrial networking protocols,can be applied in a number of industrial situations.This study also investigates the possible future development of clock synchronization techniques and technologies.

A Secure Clock Synchronization Scheme for Wireless Sensor Networks Against Malicious Attacks

This paper studies the secure and accurate clock synchronization problem for sensor networks with time-varying delays and malicious attacks.A novel clock synchronization scheme based on the attack detection mechanism,attack compensation,and maximum consensus protocol is proposed.The proposed scheme starts with the detection of the malicious attacks and the clock data under attacks is eliminated.On the basis,software clock parameters are updated so that all the nodes in the network can have the same software skew and offset,so the clock synchronization can be achieved.Furthermore,it is theoretically proved that the proposed scheme can achieve the attack detection correctly,and further can guarantee a secure and accurate clock synchronization.In addition,extensive simulations are also conducted to validate the effectiveness of the proposed scheme.

Clock auto-synchronization method for BESIII ETOF upgrade

An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （ETOF） upgrade of the Beijing Spectrometer （BESIII）. In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned~ the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square （RMS）, but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.

A high-precision synchronization circuit for clock distribution

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.

Synchronization of Fourier-Synthesized Optical Pulses to a Mode-Locked Optical Clock

A Fourier-synthesized 40-GHz optical pulse train was successfully synchronized to an 8-GHz optical clock generated from a mode-locked fiber ring laser. The measured timing jitter of the synchronization was 0.43 ps.