Active faults are a common adverse geological phenomenon that can occur during tunnel excavation and has a very negative impact on the construction and operation of the tunnel.In this paper,the grade IV rock surroundi...Active faults are a common adverse geological phenomenon that can occur during tunnel excavation and has a very negative impact on the construction and operation of the tunnel.In this paper,the grade IV rock surrounding the cross-fault tunnel with poor geological conditions has been chosen for the study.The support capacity of 2^(nd) Generation-Negative Poisson’s Ratio(2G-NPR)bolt in an active fault tunnel has been carried out on the basis of relevant results obtained from the geomechanical model test and numerical investigations of failure model for existing unsupported fault tunnel.The investigation shows that surrounding rock of the tunnel is prone to shear deformation and crack formation along the fault,as a result,the rock mass on the upper part of the fault slips as a whole.Furthermore,small-scale deformation and loss of blocks are observed around the tunnel;however,the 2G-NPR bolt support is found to be helpful in keeping the overall tunnel intact without any damage and instability.Due to the blocking effect of fault,the stress of the surrounding rock on the upper and lower parts of the fault is significantly different,and the stress at the left shoulder of the tunnel is greater than that at the right shoulder.The asymmetrical arrangement of 2G-NPR bolts can effectively control the asymmetric deformation and instability of the surrounding rock.The present numerical scheme is in good agreement with the model test results,and can reasonably reflect the stress and displacement characteristics of the surrounding rock of the tunnel.In comparison to unsupported and ordinary PR(Poisson’s Ratio)bolt support,2G-NPR bolt can effectively limit the fault slip and control the stability of the surrounding rock of the fault tunnel.The research findings may serve as a guideline for the use of 2G-NPR bolts in fault tunnel support engineering.展开更多
Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the numbe...Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.展开更多
Virtual testability demonstration test has many advantages,such as low cost,high efficiency,low risk and few restrictions.It brings new requirements to the fault sample generation.A fault sample simulation approach fo...Virtual testability demonstration test has many advantages,such as low cost,high efficiency,low risk and few restrictions.It brings new requirements to the fault sample generation.A fault sample simulation approach for virtual testability demonstration test based on stochastic process theory is proposed.First,the similarities and differences of fault sample generation between physical testability demonstration test and virtual testability demonstration test are discussed.Second,it is pointed out that the fault occurrence process subject to perfect repair is renewal process.Third,the interarrival time distribution function of the next fault event is given.Steps and flowcharts of fault sample generation are introduced.The number of faults and their occurrence time are obtained by statistical simulation.Finally,experiments are carried out on a stable tracking platform.Because a variety of types of life distributions and maintenance modes are considered and some assumptions are removed,the sample size and structure of fault sample simulation results are more similar to the actual results and more reasonable.The proposed method can effectively guide the fault injection in virtual testability demonstration test.展开更多
VLSI testing is being pushed to the high-level based technology. In thispaper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The modelprovides a text format file, which is convenien...VLSI testing is being pushed to the high-level based technology. In thispaper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The modelprovides a text format file, which is convenient and more practical for developing succeedingRegister Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and soforth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL faultmodels and super faults defined, the concurrent fault simulation algorithm is given. Thecorresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments showthat the RTL fault simulator is efficient for VLSI circuits.展开更多
基金supported by the National Natural Science Foundation of China(NSFC)(41941018)the Program of China Scholarship Council(202106430031)。
文摘Active faults are a common adverse geological phenomenon that can occur during tunnel excavation and has a very negative impact on the construction and operation of the tunnel.In this paper,the grade IV rock surrounding the cross-fault tunnel with poor geological conditions has been chosen for the study.The support capacity of 2^(nd) Generation-Negative Poisson’s Ratio(2G-NPR)bolt in an active fault tunnel has been carried out on the basis of relevant results obtained from the geomechanical model test and numerical investigations of failure model for existing unsupported fault tunnel.The investigation shows that surrounding rock of the tunnel is prone to shear deformation and crack formation along the fault,as a result,the rock mass on the upper part of the fault slips as a whole.Furthermore,small-scale deformation and loss of blocks are observed around the tunnel;however,the 2G-NPR bolt support is found to be helpful in keeping the overall tunnel intact without any damage and instability.Due to the blocking effect of fault,the stress of the surrounding rock on the upper and lower parts of the fault is significantly different,and the stress at the left shoulder of the tunnel is greater than that at the right shoulder.The asymmetrical arrangement of 2G-NPR bolts can effectively control the asymmetric deformation and instability of the surrounding rock.The present numerical scheme is in good agreement with the model test results,and can reasonably reflect the stress and displacement characteristics of the surrounding rock of the tunnel.In comparison to unsupported and ordinary PR(Poisson’s Ratio)bolt support,2G-NPR bolt can effectively limit the fault slip and control the stability of the surrounding rock of the fault tunnel.The research findings may serve as a guideline for the use of 2G-NPR bolts in fault tunnel support engineering.
文摘Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.
基金National Natural Science Foundation of China(51105369)
文摘Virtual testability demonstration test has many advantages,such as low cost,high efficiency,low risk and few restrictions.It brings new requirements to the fault sample generation.A fault sample simulation approach for virtual testability demonstration test based on stochastic process theory is proposed.First,the similarities and differences of fault sample generation between physical testability demonstration test and virtual testability demonstration test are discussed.Second,it is pointed out that the fault occurrence process subject to perfect repair is renewal process.Third,the interarrival time distribution function of the next fault event is given.Steps and flowcharts of fault sample generation are introduced.The number of faults and their occurrence time are obtained by statistical simulation.Finally,experiments are carried out on a stable tracking platform.Because a variety of types of life distributions and maintenance modes are considered and some assumptions are removed,the sample size and structure of fault sample simulation results are more similar to the actual results and more reasonable.The proposed method can effectively guide the fault injection in virtual testability demonstration test.
文摘VLSI testing is being pushed to the high-level based technology. In thispaper a Verilog Register transfer level Model (VRM) for integrated circuits is proposed. The modelprovides a text format file, which is convenient and more practical for developing succeedingRegister Transfer Level (RTL) test tools, such as fault simulation, test pattern generation and soforth. Based on the VRM, an RTL concurrent fault simulation approach is presented. After RTL faultmodels and super faults defined, the concurrent fault simulation algorithm is given. Thecorresponding RTL concurrent fault simulator, VFSim, was implemented. The initial experiments showthat the RTL fault simulator is efficient for VLSI circuits.
