Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a sou...Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a source ALU using target ALU.The source ALUs and the target ALUs are all represented by the general ALUs and the mapping rules are applied in the algorithm.The mapping rules are described in a table fashion.The graph clustering algorithm is a branch and bound algorithm based on the graph formulation of the mapping algorithm.The mapping algorithm suits well mapping of regularly structured data path.Comparisons are made between the experimental results generated by 1 greedy algorithm and graphclustering algorithm,showing the feasibility of presented algorithm.展开更多
Clustered architecture is selected for high level synthesis,and a simultaneous partitioning and scheduling algorithm are proposed.Compared with traditional methods,circuit performance can be improved.Experiments show ...Clustered architecture is selected for high level synthesis,and a simultaneous partitioning and scheduling algorithm are proposed.Compared with traditional methods,circuit performance can be improved.Experiments show the efficiency of the method.展开更多
This paper studies the realization of the high level synthesis fromsystem behavioral (algorithmic or functional) description of circuits to structuraldescription of RTL and logic level. Based on Xilinx-FPGA libraryl t...This paper studies the realization of the high level synthesis fromsystem behavioral (algorithmic or functional) description of circuits to structuraldescription of RTL and logic level. Based on Xilinx-FPGA libraryl the structural description is mapped to technology-dependent ASIC, and FPGA chips are generated.The main points in this paper include the technical decision of each subsystem in aVHDL high level synthesis system HLS/BIT. The system is realized on SUN SPARC2, and correct running results are given.展开更多
In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at h...In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.展开更多
文摘Register transfer level mapping (RTLM) algorithm for technology mapping at RT level is presented,which supports current design methodologies using high level design and design reuse.The mapping rules implement a source ALU using target ALU.The source ALUs and the target ALUs are all represented by the general ALUs and the mapping rules are applied in the algorithm.The mapping rules are described in a table fashion.The graph clustering algorithm is a branch and bound algorithm based on the graph formulation of the mapping algorithm.The mapping algorithm suits well mapping of regularly structured data path.Comparisons are made between the experimental results generated by 1 greedy algorithm and graphclustering algorithm,showing the feasibility of presented algorithm.
文摘Clustered architecture is selected for high level synthesis,and a simultaneous partitioning and scheduling algorithm are proposed.Compared with traditional methods,circuit performance can be improved.Experiments show the efficiency of the method.
文摘This paper studies the realization of the high level synthesis fromsystem behavioral (algorithmic or functional) description of circuits to structuraldescription of RTL and logic level. Based on Xilinx-FPGA libraryl the structural description is mapped to technology-dependent ASIC, and FPGA chips are generated.The main points in this paper include the technical decision of each subsystem in aVHDL high level synthesis system HLS/BIT. The system is realized on SUN SPARC2, and correct running results are given.
基金the Natural Science Foundation of Hei- longjiang Province, China (F2004-17).
文摘In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.
