With the development of Ethernet systems and the growing capacity of modem silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardwa...With the development of Ethernet systems and the growing capacity of modem silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethemet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Intemet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system＇s throughput. Our simulation results showed that the maximum throughput of Ethemet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethemet, and that using only one chip can realize that many electronic devices access to the Intemet directly and get high performance.展开更多
This paper presents a macroblock-level (MB-level) decoding and deblocking method for supporting the flexible macroblock ordering (FMO) and arbitrary slice ordering (ASO) bit streams in H.264 decoder and its SOC/ASIC i...This paper presents a macroblock-level (MB-level) decoding and deblocking method for supporting the flexible macroblock ordering (FMO) and arbitrary slice ordering (ASO) bit streams in H.264 decoder and its SOC/ASIC implementation. By searching the slice containing the current macroblock in the bit stream and switching slices correctly, MBs can be decoded in the raster scan order, while the decoding process can immediately begin as long as the slice containing the current MB is available. This architectural modification enables the MB-level decoding and deblocking 3-stage pipeline, and saves about 20% of SDRAM bandwidth. Implementation results showed that the design achieves real-time decoding of 1080HD (1920×1088@30 fps) at a system clock of 166 MHz.展开更多
The growing complexity of System on Chip （SOC） requres a system level specicanon and design approach. High-level languages such as C＋＋/SystemC can play multiple roles in system design as target languages. There ar...The growing complexity of System on Chip （SOC） requres a system level specicanon and design approach. High-level languages such as C＋＋/SystemC can play multiple roles in system design as target languages. There are many practical problems in the application of object-oriented methods for this goal. Based on the analysis of traditional and system-level design methodology, a new object-oriented SOC design methodology with object-oriented design patterns is proposed, which emphasizes high-level design and verification. Aiming at the final goal of developing design patterns specific to SOC design, the reuse of design patterns in SOC systems and the capability of new SOC design patterns are discussed. With the illustration of some concrete examples of SOC design patterns, the application of object-oriented design methodology in the SOC design process is presented.展开更多
集成电路制造技术的迅速发展已经可以把一个完整的电子系统集成到一个芯片上即所谓的系统级芯片 (Sys tem on Chip ,简称SoC)。传统的设计方法是将硬件和软件分开来设计的 ,在硬件设计完成并生产出样片后才能调试软件。本文介绍了针对...集成电路制造技术的迅速发展已经可以把一个完整的电子系统集成到一个芯片上即所谓的系统级芯片 (Sys tem on Chip ,简称SoC)。传统的设计方法是将硬件和软件分开来设计的 ,在硬件设计完成并生产出样片后才能调试软件。本文介绍了针对于系统级芯片设计的软硬件协同设计技术 (co design)的概念和设计流程 。展开更多
随着SoC(System on Chip)应用越来越广泛,现代电子系统大多以SoC为基础进行设计。首先调研目前的SoC电子系统设计课程,在此基础上介绍了内容上和教学模式上具有一定创新的现代电子系统设计相关课程,并详细介绍了课程的教学指导思想、教...随着SoC(System on Chip)应用越来越广泛,现代电子系统大多以SoC为基础进行设计。首先调研目前的SoC电子系统设计课程,在此基础上介绍了内容上和教学模式上具有一定创新的现代电子系统设计相关课程,并详细介绍了课程的教学指导思想、教学内容和教学模式及课程开设的效果。展开更多
文摘With the development of Ethernet systems and the growing capacity of modem silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethemet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Intemet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system＇s throughput. Our simulation results showed that the maximum throughput of Ethemet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethemet, and that using only one chip can realize that many electronic devices access to the Intemet directly and get high performance.
基金Project (No. 2002AA1Z1190) supported by the National Hi-Tech Research and Development Program (863) of China
文摘This paper presents a macroblock-level (MB-level) decoding and deblocking method for supporting the flexible macroblock ordering (FMO) and arbitrary slice ordering (ASO) bit streams in H.264 decoder and its SOC/ASIC implementation. By searching the slice containing the current macroblock in the bit stream and switching slices correctly, MBs can be decoded in the raster scan order, while the decoding process can immediately begin as long as the slice containing the current MB is available. This architectural modification enables the MB-level decoding and deblocking 3-stage pipeline, and saves about 20% of SDRAM bandwidth. Implementation results showed that the design achieves real-time decoding of 1080HD (1920×1088@30 fps) at a system clock of 166 MHz.
文摘The growing complexity of System on Chip （SOC） requres a system level specicanon and design approach. High-level languages such as C＋＋/SystemC can play multiple roles in system design as target languages. There are many practical problems in the application of object-oriented methods for this goal. Based on the analysis of traditional and system-level design methodology, a new object-oriented SOC design methodology with object-oriented design patterns is proposed, which emphasizes high-level design and verification. Aiming at the final goal of developing design patterns specific to SOC design, the reuse of design patterns in SOC systems and the capability of new SOC design patterns are discussed. With the illustration of some concrete examples of SOC design patterns, the application of object-oriented design methodology in the SOC design process is presented.
文摘集成电路制造技术的迅速发展已经可以把一个完整的电子系统集成到一个芯片上即所谓的系统级芯片 (Sys tem on Chip ,简称SoC)。传统的设计方法是将硬件和软件分开来设计的 ,在硬件设计完成并生产出样片后才能调试软件。本文介绍了针对于系统级芯片设计的软硬件协同设计技术 (co design)的概念和设计流程 。
