First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implem...First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.展开更多
随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相...随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相应测试方法研究。提出了一种高效的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法。该方法以ZYNQ MPSOC为核心,设计了一种直达应用层面的系统级测试装置,从而减少了与物理层直接交互的行为,有效降低了测试装置及程序开发难度。经试验验证,提出的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法能够用于以太网PHY芯片测试。展开更多
由于传统无迹卡尔曼滤波估算方法具有局限性,为了能准确估算动力电池荷电状态(state of charge,SOC),提出了一种基于无迹卡尔曼粒子滤波的动力电池SOC估算方法.以三元锂电池为研究对象,建立了电池二阶RC等效电路模型,通过对电池进行充...由于传统无迹卡尔曼滤波估算方法具有局限性,为了能准确估算动力电池荷电状态(state of charge,SOC),提出了一种基于无迹卡尔曼粒子滤波的动力电池SOC估算方法.以三元锂电池为研究对象,建立了电池二阶RC等效电路模型,通过对电池进行充放电试验辨识出模型参数,并验证模型准确性.采集了实际工况下的电池数据,分别用无迹卡尔曼滤波算法、粒子滤波算法和无迹卡尔曼粒子滤波算法估算电池SOC,在MATLAB中进行了仿真试验,并对估算的电池SOC进行比较.结果表明:无迹卡尔曼粒子滤波算法可以快速准确地估算出电池SOC,误差小于2.5%,优于另外2种算法.展开更多
文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比...文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比较,结果表明,所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE(hFSE)架构实现在SoC的处理系统和可编程逻辑块(programmable logic,PL)上,通过高级可扩展接口(Advanced eXtensible Interface 4,AXI4)总线连接SoC的处理系统和可编程逻辑块。算法测试显示,FSE算法在非均匀数据分布和大数据量情况下,具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现,其中包括1个可配置的缓冲模块,将比特流作为单字节或双字节配置输出到8 bit位宽4096深度或16 bit位宽2048深度的块随机访问存储器(block random access memory,BRAM)中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。展开更多
In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant...In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..展开更多
文摘First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.
文摘由于传统无迹卡尔曼滤波估算方法具有局限性,为了能准确估算动力电池荷电状态(state of charge,SOC),提出了一种基于无迹卡尔曼粒子滤波的动力电池SOC估算方法.以三元锂电池为研究对象,建立了电池二阶RC等效电路模型,通过对电池进行充放电试验辨识出模型参数,并验证模型准确性.采集了实际工况下的电池数据,分别用无迹卡尔曼滤波算法、粒子滤波算法和无迹卡尔曼粒子滤波算法估算电池SOC,在MATLAB中进行了仿真试验,并对估算的电池SOC进行比较.结果表明:无迹卡尔曼粒子滤波算法可以快速准确地估算出电池SOC,误差小于2.5%,优于另外2种算法.
文摘文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比较,结果表明,所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE(hFSE)架构实现在SoC的处理系统和可编程逻辑块(programmable logic,PL)上,通过高级可扩展接口(Advanced eXtensible Interface 4,AXI4)总线连接SoC的处理系统和可编程逻辑块。算法测试显示,FSE算法在非均匀数据分布和大数据量情况下,具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现,其中包括1个可配置的缓冲模块,将比特流作为单字节或双字节配置输出到8 bit位宽4096深度或16 bit位宽2048深度的块随机访问存储器(block random access memory,BRAM)中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。
文摘In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..
