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Dynamic Measurement of Task Scheduling Algorithm in Multi-Processor System 被引量:1
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作者 XIE Ying WU Jinzhao +1 位作者 CHEN Jianying CUI Mengtian 《Journal of Shanghai Jiaotong university(Science)》 EI 2019年第3期372-380,共9页
It is important to evaluate function behaviors and performance features of task scheduling algorithm in the multi-processor system.A novel dynamic measurement method(DMM)was proposed to measure the task scheduling alg... It is important to evaluate function behaviors and performance features of task scheduling algorithm in the multi-processor system.A novel dynamic measurement method(DMM)was proposed to measure the task scheduling algorithm’s correctness and dependability.In a multi-processor system,task scheduling problem is represented by a combinatorial evaluation model,interactive Markov chain(IMC),and solution space of the algorithm with time and probability metrics is described by action-based continuous stochastic logic(aCSL).DMM derives a path by logging runtime scheduling actions and corresponding times.Through judging whether the derived path can be received by task scheduling IMC model,DMM analyses the correctness of algorithm.Through judging whether the actual values satisfy label function of the initial state,DMM analyses the dependability of algorithm.The simulation shows that DMM can effectively characterize the function behaviors and performance features of task scheduling algorithm. 展开更多
关键词 MULTI-PROCESSOR task scheduling algorithm IMC aCSL dynamic measurement
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Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint
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作者 Ying-Lin Zhao Jian-Lei Yang +2 位作者 Wei-Sheng Zhao Aida Todri-Sanial Yuan-Qing Cheng 《Journal of Computer Science & Technology》 SCIE EI CSCD 2018年第5期966-983,共18页
Thanks to the emerging 3D integration technology, The multiprocessor system on chips (MPSoCs) can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up ... Thanks to the emerging 3D integration technology, The multiprocessor system on chips (MPSoCs) can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise (PSN) interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network (PDN) solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN. 展开更多
关键词 MPSoCs power supply noise (PSN) power delivery network (PDN) task scheduling algorithm TEMPERATURE 3D
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