Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effec...Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOl device and their corresponding advantages and disadvantages are studied in detail. Under 0.13μm bulk silicon and SOl process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout （protection ring for bulk silicon DFF, T-gate for SO! DFF）, while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design.展开更多
A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the...A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.展开更多
A novel off-state gate RHBD technique to mitigate the single-event transient(SET)in the differential data path of analog circuit is demonstrated in this paper.Simulation results present that this off-state gate techni...A novel off-state gate RHBD technique to mitigate the single-event transient(SET)in the differential data path of analog circuit is demonstrated in this paper.Simulation results present that this off-state gate technique could exploit charge sharing in differential circuits and reduce differential mode voltage perturbation effectively.It is indicated that this technique is more effective to mitigate SET than the differential charge cancellation(DCC)technique with less penalty.展开更多
文摘Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOl device and their corresponding advantages and disadvantages are studied in detail. Under 0.13μm bulk silicon and SOl process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout （protection ring for bulk silicon DFF, T-gate for SO! DFF）, while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60836004 and 60906014)Hunan Provincial Innovation Foundation For Postgraduate (Grant No. CX2011B026)
文摘A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.
基金supported by the State Key Program of the National Natural Science Foundation of China(Grant No.60836004)the National Natural Science Foundation of China(Grant No.61376109)
文摘A novel off-state gate RHBD technique to mitigate the single-event transient(SET)in the differential data path of analog circuit is demonstrated in this paper.Simulation results present that this off-state gate technique could exploit charge sharing in differential circuits and reduce differential mode voltage perturbation effectively.It is indicated that this technique is more effective to mitigate SET than the differential charge cancellation(DCC)technique with less penalty.
