Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...

Comparison of Temperature Field Distribution between Cement Preclinkering Technology and Cement Precalcining Technology

Through the comparison of calcination conditions between cement preclinkering technology and cement precalcining technology,we studied the characteristics of temperature field distribution of cement preclinkering technology systems including cyclone preheater,preclinkering furnace,and rotary kiln.We used numericalsimulation method to obtain data of temperature field distribution.Some results are found by system study.The ratio of tailcoalof cement preclinkering technology is about 70%,and raw mealtemperature can reach 1070 ℃.Shorter L/D kiln type of preclinkering technology can obtain more stable calcining zone temperature.The highest solid temperature of cement preclinkering technology is higher than 80 ℃,and high temperature region（〉1450 ℃）length is 2 times,which is beneficialfor calcining clinker and higher clinker quality.So cement preclinkering technology can obtain more performance temperature filed,which improves both the solid-phase reaction and liquid-phase reaction.

Fault self-repair strategy based on evolvable hardware and reparation balance technology

In the face of harsh natural environment applications such as earth-orbiting and deep space satellites, underwater sea vehicles, strong electromagnetic interference and temperature stress,the circuits faults appear easily. Circuit faults will inevitably lead to serious losses of availability or impeded mission success without self-repair over the mission duration. Traditional fault-repair methods based on redundant fault-tolerant technique are straightforward to implement, yet their area, power and weight cost can be excessive. Moreover they utilize all plug-in or component level circuits to realize redundant backup, such that their applicability is limited. Hence, a novel selfrepair technology based on evolvable hardware（EHW） and reparation balance technology（RBT） is proposed. Its cost is low, and fault self-repair of various circuits and devices can be realized through dynamic configuration. Making full use of the fault signals, correcting circuit can be found through EHW technique to realize the balance and compensation of the fault output-signals. In this paper, the self-repair model was analyzed which based on EHW and RBT technique, the specific self-repair strategy was studied, the corresponding self-repair circuit fault system was designed, and the typical faults were simulated and analyzed which combined with the actual electronic devices. Simulation results demonstrated that the proposed fault self-repair strategy was feasible. Compared to traditional techniques, fault self-repair based on EHW consumes fewer hardware resources, and the scope of fault self-repair was expanded significantly.

Optimal design of RTCs in digital circuit fault self-repair based on global signal optimization

Since digital circuits have been widely and thoroughly applied in various fields, electronic systems are increasingly more complicated and require greater reliability. Faults may occur in electronic systems in complicated environments. If immediate field repairs are not made on the faults, electronic systems will not run normally, and this will lead to serious losses. The traditional method for improving system reliability based on redundant fault-tolerant technique has been unable to meet the requirements. Therefore, on the basis of(evolvable hardware)-based and(reparation balance technology)-based electronic circuit fault self-repair strategy proposed in our preliminary work, the optimal design of rectification circuits(RTCs) in electronic circuit fault self-repair based on global signal optimization is deeply researched in this paper. First of all, the basic theory of RTC optimal design based on global signal optimization is proposed. Secondly, relevant considerations and suitable ranges are analyzed. Then, the basic flow of RTC optimal design is researched. Eventually, a typical circuit is selected for simulation verification, and detailed simulated analysis is made on five circumstances that occur during RTC evolution. The simulation results prove that compared with the conventional design method based RTC, the global signal optimization design method based RTC is lower in hardware cost, faster in circuit evolution, higher in convergent precision, and higher in circuit evolution success rate. Therefore, the global signal optimization based RTC optimal design method applied in the electronic circuit fault self-repair technology is proven to be feasible, effective, and advantageous.