Ultra-thin-body (UTB) In0.53Ga0.47As-on-insulator (In0.53Ga0.47As-OI) structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nm...Ultra-thin-body (UTB) In0.53Ga0.47As-on-insulator (In0.53Ga0.47As-OI) structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors (nMOSFETs) are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability (PBTI) and hot carrier injection (HCI) characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.展开更多
A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability(PBTI) stress ...A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability(PBTI) stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.展开更多
The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of Vth shift induced by NBT1. However, this recovery is unstab...The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of Vth shift induced by NBT1. However, this recovery is unstable. The original degradation reappears soon after reapplication of the NBT stress condition. Hydrogen-related species play a key role during a device's NBT degradation. Experimental results show that the diffusion species are neutral, they repassivate Si dangling bond which is independent of the gate voltage polaxity. In addition to the diffusion towards gate oxide, hydrogen diffusion to Si-substrate must be taken into account for it also has important influence on device degradation during NBT stress.展开更多
This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large g...This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.展开更多
A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking fro...A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking from 100 nm to 30 nm,both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better.Moreover,the channel length dependence on NBTI is more serious than that on PBTI.Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device,a physical mechanism of the channel length dependence on NBTI/PBTI is proposed.Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue,while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs.The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process.展开更多
The effect of the static negative bias temperature (NBT) stress on a p-channel power metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated by experiment and simulation. The time evolution of t...The effect of the static negative bias temperature (NBT) stress on a p-channel power metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated by experiment and simulation. The time evolution of the negative bias temperature instability (NBTI) degradation has the trend predicted by the reaction-diffusion (R-D) model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R-D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.展开更多
The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias tempera...The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electro,hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.展开更多
Hot carrier injection (HCI) at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-...Hot carrier injection (HCI) at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.展开更多
A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID-VD characterization...A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID-VD characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous onthe-fly method. It is found that both reaction-diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90℃ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction-diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction-diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.展开更多
Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. ...Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.展开更多
This paper studies negative bias temperature instability (NBTI) under alternant and alternating current (AC) stress. Under alternant stress, the degradation smaller than that of single negative stress is obtained....This paper studies negative bias temperature instability (NBTI) under alternant and alternating current (AC) stress. Under alternant stress, the degradation smaller than that of single negative stress is obtained. The smaller degradation is resulted from the recovery of positive stress. There are two reasons for the recovery. One is the passivation of H dangling bonds, and another is the detrapping of charges trapped in the oxide. Under different frequencies of AC stress, the parameters all show regular degradation, and also smaller than that of the direct current stress. The higher the frequency is, the smaller the degradation becomes. As the negative stress time is too small under higher frequency, the deeper defects are hard to be filled in. Therefore, the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.展开更多
The exponent n of the generation of an interface trap (Nit), which contributes to the power-law negative bias temperature instability (NBTI) degradation, and the exponent’s time evolution are investigated by simu...The exponent n of the generation of an interface trap (Nit), which contributes to the power-law negative bias temperature instability (NBTI) degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.展开更多
In this article,the body bias dependence of the bias temperature instability(BTI)in bulk FinFETs is experimentally studied,under different test conditions for the first time.In contrast to the traditional understandin...In this article,the body bias dependence of the bias temperature instability(BTI)in bulk FinFETs is experimentally studied,under different test conditions for the first time.In contrast to the traditional understanding that changing body bias has little impact on BTI degradation in FinFETs due to its weak body effect,it is observed that it actually has non-negligible impacts.And a forward body bias(FBB)can reduce the BTI degradation in FinFETs,which is opposite with the trend in planar devices.The underlying physics is found due to the trade-off between two competing factors.The results are helpful for understanding and modeling reliability in FinFETs.展开更多
The positive bias temperature instability(PBTI) degradations of high-k/metal gate(HK/MG) n MOSFETs with thin TiN capping layers(1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy di...The positive bias temperature instability(PBTI) degradations of high-k/metal gate(HK/MG) n MOSFETs with thin TiN capping layers(1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI(90℃,125℃, 160℃) are studied and activation energy(Ea) values(0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness(EOT) values of two TiN thickness values are almost similar(0.85 nm and 0.87 nm), the 2.4-nm TiN one(thicker Ti N capping layer) shows better PBTI reliability(13.41% at 0.9 V, 90℃, 1000 s). This is due to the better interfacial layer/high-k(IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.展开更多
The effect of negative bias temperature instability (NBTI) on a single event transient (SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that...The effect of negative bias temperature instability (NBTI) on a single event transient (SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.展开更多
Positive bias temperature instability(PBTI) characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage sh...Positive bias temperature instability(PBTI) characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.展开更多
In this work,the anomalous transport driven by the ion temperature gradient instability is investigated in an anisotropic deuterium-tritium(D-T)plasma.The anisotropic factorα,defined as the ratio of perpendicular tem...In this work,the anomalous transport driven by the ion temperature gradient instability is investigated in an anisotropic deuterium-tritium(D-T)plasma.The anisotropic factorα,defined as the ratio of perpendicular temperature to parallel temperature,is introduced to describe the temperature anisotropy in the equilibrium distribution function.The linear dispersion relation in local kinetic limit is derived,and then numerically evaluated to study the dependence of mode frequency on the anisotropic factorαof D and the fraction of T particleεTby choosing three sets of typical parameters,denoted as the cyclone base case,ITER and CFETR cases.Based on the linear results,the mixing length model approximation is adopted to analyze the quasi-linear particle and energy fluxes for D and T.It is found that choosing smallαand largeεTis beneficial for the confinement of particle and energy for D and T.This work may be helpful for the estimation of turbulent transport level in the ITER and CFETR devices.展开更多
Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing ga...Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.展开更多
Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature (NBT-PBT-NBT) stress conditions are investigated in this paper. It is found that for all de...Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature (NBT-PBT-NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.展开更多
In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors(VDMOSFETs) subjected to negative bias tempe...In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors(VDMOSFETs) subjected to negative bias temperature(NBT)stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps(permanent component).Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.展开更多
基金Supported by the National Program on Key Basic Research Project of China under Grant No 2011CBA00607the National Natural Science Foundation of China under Grant Nos 61106089 and 61376097the Zhejiang Provincial Natural Science Foundation of China under Grant No LR14F040001
文摘Ultra-thin-body (UTB) In0.53Ga0.47As-on-insulator (In0.53Ga0.47As-OI) structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors (nMOSFETs) are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability (PBTI) and hot carrier injection (HCI) characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.
基金Project supported by the National Science&Technology Major Projects of the Ministry of Science and Technology of China(Grant No.2009ZX02035)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability(PBTI) stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.
基金Project supported by the National Natural Science Foundation of China (Grant No 60206006), the Hi-Tech Research & Development Program of China (Grant No 2004AA1Z1070) and the Key Project of Chinese Ministry of Education (Grant No 104172).
文摘The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of Vth shift induced by NBT1. However, this recovery is unstable. The original degradation reappears soon after reapplication of the NBT stress condition. Hydrogen-related species play a key role during a device's NBT degradation. Experimental results show that the diffusion species are neutral, they repassivate Si dangling bond which is independent of the gate voltage polaxity. In addition to the diffusion towards gate oxide, hydrogen diffusion to Si-substrate must be taken into account for it also has important influence on device degradation during NBT stress.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60736033 and 60376024)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (Grant No. 2007BAK25B03)
文摘This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.
基金the Science and Technology Program of Beijing Municipal Science and Technology Commission,China(Grant No.Z201100004220001)the National Major Project of Science and Technology of China(Grant No.2017ZX02315001)the Opening Project of Key Laboratory of Microelectronic Devices&Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences(Grant Nos.Y9YS05X002 and E0YS01X001).
文摘A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking from 100 nm to 30 nm,both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better.Moreover,the channel length dependence on NBTI is more serious than that on PBTI.Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device,a physical mechanism of the channel length dependence on NBTI/PBTI is proposed.Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue,while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs.The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant No.61106106)
文摘The effect of the static negative bias temperature (NBT) stress on a p-channel power metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated by experiment and simulation. The time evolution of the negative bias temperature instability (NBTI) degradation has the trend predicted by the reaction-diffusion (R-D) model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R-D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.
基金Project supported by the National Natural Science Foundation of China (Grant Nos 60376024,60736033 and 60506020)the National High Technology Research and Development Program of China (Grant No 2003AA1Z1630)
文摘The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electro,hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.
基金Project supported by the National Natural Science Foundation of China (Grant No 60206006). the Program for New Century Excellent Talents of Ministry of Education of China (Grant No 681231366). the National Defense Pre-Research Foundation of China (Grant No 51408010305DZ0168) and the Key Project of Chinese Ministry of Education (Grant No 104172).
文摘Hot carrier injection (HCI) at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.
文摘A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID-VD characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous onthe-fly method. It is found that both reaction-diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90℃ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction-diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction-diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.
基金Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003the National Natural Science Foundation of China under Grant No 61504165the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of Chinese Academy of Sciences
文摘Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.
基金Project supported by the National Key Science and Technology Special Project,China (Grant No. 2008ZX01002-002)the Fundamental Research Funds for the Central Universities,China (Grant No. JY10000904009)the Major Program and State Key Program of the National Natural Science Foundation of China (Grant Nos. 60890191 and 60736033)
文摘This paper studies negative bias temperature instability (NBTI) under alternant and alternating current (AC) stress. Under alternant stress, the degradation smaller than that of single negative stress is obtained. The smaller degradation is resulted from the recovery of positive stress. There are two reasons for the recovery. One is the passivation of H dangling bonds, and another is the detrapping of charges trapped in the oxide. Under different frequencies of AC stress, the parameters all show regular degradation, and also smaller than that of the direct current stress. The higher the frequency is, the smaller the degradation becomes. As the negative stress time is too small under higher frequency, the deeper defects are hard to be filled in. Therefore, the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant No.61106106)the Fundamental Research Funds for the Central Universities,China(Grant No.K50511250008)
文摘The exponent n of the generation of an interface trap (Nit), which contributes to the power-law negative bias temperature instability (NBTI) degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.
基金supported by NSFC(61874005,61927901)the 111 Project(B18001).
文摘In this article,the body bias dependence of the bias temperature instability(BTI)in bulk FinFETs is experimentally studied,under different test conditions for the first time.In contrast to the traditional understanding that changing body bias has little impact on BTI degradation in FinFETs due to its weak body effect,it is observed that it actually has non-negligible impacts.And a forward body bias(FBB)can reduce the BTI degradation in FinFETs,which is opposite with the trend in planar devices.The underlying physics is found due to the trade-off between two competing factors.The results are helpful for understanding and modeling reliability in FinFETs.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘The positive bias temperature instability(PBTI) degradations of high-k/metal gate(HK/MG) n MOSFETs with thin TiN capping layers(1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI(90℃,125℃, 160℃) are studied and activation energy(Ea) values(0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness(EOT) values of two TiN thickness values are almost similar(0.85 nm and 0.87 nm), the 2.4-nm TiN one(thicker Ti N capping layer) shows better PBTI reliability(13.41% at 0.9 V, 90℃, 1000 s). This is due to the better interfacial layer/high-k(IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.
基金Project supported by the Key Program of the National Natural Science Foundation of China(No.60836004)the National Natural Science Foundation of China(Nos.61006070,61076025)
文摘The effect of negative bias temperature instability (NBTI) on a single event transient (SET) has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.
基金Project supported by the Important National Science&Technology Specific Projects(No.2009ZX02035)the National Natural Science Foundation of China(Nos.61176091,61306129)
文摘Positive bias temperature instability(PBTI) characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.
基金supported by the National MCF Energy R&D Program of China(No.2019YFE03060000)National Natural Science Foundation of China(Nos.12005063,12175228,11875131 and 11675053)。
文摘In this work,the anomalous transport driven by the ion temperature gradient instability is investigated in an anisotropic deuterium-tritium(D-T)plasma.The anisotropic factorα,defined as the ratio of perpendicular temperature to parallel temperature,is introduced to describe the temperature anisotropy in the equilibrium distribution function.The linear dispersion relation in local kinetic limit is derived,and then numerically evaluated to study the dependence of mode frequency on the anisotropic factorαof D and the fraction of T particleεTby choosing three sets of typical parameters,denoted as the cyclone base case,ITER and CFETR cases.Based on the linear results,the mixing length model approximation is adopted to analyze the quasi-linear particle and energy fluxes for D and T.It is found that choosing smallαand largeεTis beneficial for the confinement of particle and energy for D and T.This work may be helpful for the estimation of turbulent transport level in the ITER and CFETR devices.
文摘Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.
基金Project supported by the National Natural Science Foundation of China (Grant No 60206006), the Program for New Century Excellent Talents of Ministry of Education of China (Grant No 681231366), the National Defense Pre-Research Foundation of China (Grant No 51308040103) and the Key Project of Chinese Ministry of Education (Grant No 104172).
文摘Degradation characteristics of PMOSFETs under negative bias temperature-positive bias temperature-negative bias temperature (NBT-PBT-NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.
基金Project supported by the Fund from the Ministry of Education,Science and Technological Development of the Republic of Serbia(Grant Nos.OI-171026 and TR-32026)the Ei PCB Factory,Ni
文摘In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors(VDMOSFETs) subjected to negative bias temperature(NBT)stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps(permanent component).Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.